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rev 1 january 2006 www.semtec h.com xe8806a/xe8807a xe8806a and xe8807a ultra low-power low-voltage radio machines general description the xe8806a and xe8807a are ultra low-power low- voltage microcontroller based radio machines. they include the revolutionary bitjockey?, uart type of peripheral specialized for radio communication. the xe8806a and xe8807a are available with on chip rom or multiple-time-programmable (mtp) program memory. key product features ? ultra low-power mcu, up to 7 mips ? 300 ua at 1 mips operation ? 6 ua at 32 khz operation ? 1 ua time keeping ? low-voltage operation (1.2 - 5.5 v supply voltage) ? 22 kb (8 kw) rom/mtp (xe8806a) 11 kb (4kw) mtp (xe8807a) ? 520 b ram ? 4 counters ? pwm, uart, bitjockey? ? analog matrix switching ? 4 low-power analog comparators ? independant rc and crystal oscillators ? 5 reset, 15 interrupt, 8 event sources ? 100 years mtp flash retention at 55c applications ? rf companion chip ? rf system supervisor ? portable, battery operated instruments ? metering ? remote control ? hvac control ordering information product temperature range memory type package xe8806ami000 -40c to 85 c mtp die XE8806AMI026LF -40c to 85 c mtp tqfp32 xe8806ari000 -40c to 125c rom die xe8806ari026lf -40c to 125c rom tqfp32 xe8807ami000 -40c to 85 c mtp die xe8807ami026lf -40c to 85 c mtp tqfp32 xe8806a radio machine
? semtech 2006 www.semtech.com xe8806a/xe8807a table of contents chapter title 1. general overview 2. xe8806a and xe8807a performance 3. cpu 4. memory mapping 5. low power modes 6. reset generator 7. clock generation 8. interrupt handler 9. event handler 10. low power ram 11. port a 12. port b 13. port d 14. radio asynchronous receiver/transmitter (bitjockey?) 15. universal asynchronous receiver/transmitter (uart) 16. universal synchronous receiver/transmitter (usrt) 17. counters/pwm 18. the voltage level detector 19. low power comparators 20. dimensions
? semtech 2006 www.semtech.com 1-1 xe8806a/xe8807a 1. general overview 1.1 top schematic 1-2 1.2 pin map 1-4 1.2.1 tqfp-32 1-4 1.2.2 so-28 1-4 1.2.3 so-24 1-5 1.2.4 bare die xe8806a 1-6 1.2.5 bare die xe8807a 1-7 1.3 pin assignment 1-7
? semtech 2006 www.semtech.com 1-2 xe8806a/xe8807a 1.1 top schematic the top level block schematic of the circuit is shown in figure 1-1. the heart of the circuit consists of the coolrisc816 cpu (central processing unit) core. this core includes an 8x8 multiplier and 16 internal registers. the bus controller generates all control signals for acce ss to all data registers ot her than the cpu internal registers. the reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained in its control registers. possible reset sources are the power-on-reset (por), the external pin nreset, the watchdog (wd), a bus error detected by the bus c ontroller or a programmable pattern on port a. the clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. the clock can be generated from the rc o scillator (this is the start-up condition), the crystal oscillator (xtal) or an external cl ock source (given on the xin pin). the test controller generates all set-up signals for different te st modes. in normal operation, it is used as a set of 8 low power ram. if power consumption is important for the application, the variables that need to be accessed frequently should be stored in these r egisters rather than in the ram. the irq handler routes the interrupt signals of the different peripherals to the irq inputs of the cpu core. it allows masking of the interrupt sources and it flags which interrupt source is active. events are generally used to restart the processor after a ha lt period without jumping to a specified address, i.e. the program execution resumes with t he instruction following the halt inst ruction. the evn handler routes the event signals of the different peripheral s to the evn inputs of the cpu core. it allows masking of the event sources and it flags which event source is active. the port b is an 8 bit parallel io port with analog capabilities. the usrt, uart, pwm and cmpd blocks also make use of this port. the instruction memory is a 22-bit wide flash or rom memory depending on the circuit version. in case of the rom version, the vpp pin is not used. the maximal number of instructions in the xe8806a is 8192. the maximal number of instructions in the xe8807a is 4096. the data memory on this product is a 512 byte sram. the port a is an 8 bit parallel input port. it can also generat e interrupts, events or a reset. it can be used to input external clocks for the ti mer/counter/pwm block. the port d is a general purpose 8 bit parallel io port. the usrt (universal synchronous receiver/transmitter) cont ains some simple hardware functions in order to simplify the software implementati on of a synchronous serial link. the uart (universal asynchronous receiver/transmitte r) contains a full hardware implementation of the asynchronous serial link. the rfif interface is a serial interface dedicated to comm unication with rf circuits. from the cpu side, it very much looks like an ordinary uart but it also implem ents low level coding/decoding and frame synchronisation. the input/output pins are multiplexed on port d. the counters/timers/pwm can take its clocks from inte rnal or external sources (on port a) and can generate interrupts or events. the pwm is output on port b. the vld (voltage level detector) detects the battery end of life with respect to a programmable threshold. the cmpd contains a 4 channel comparator. it is intended to monitor analog or digital signals whilst having a very low power consumption.
? semtech 2006 www.semtech.com 1-3 xe8806a/xe8807a instruction memory b u s c o n t r o l l e r test controller reset block wd clock generation/ power management vreg xtal rc cpu coolrisc816 8 x 8 multiplier 16 cpu registers irq handling evn handling port b 8 data registers port a usrt port d address control datain dataout reset control clocks test control irq evn vpp vbat vss nreset xin xout vreg test pb(7:0) pa(7:0) pd(7:0) data memory uart counters timers pw m vld cmpd pb(5:4) pb(7:6) pa(3:0) pb(1:0) pb(7:4) por rfif bitjockey pd(3:0) figure 1-1. block schematic of the xe8806a and xe8807a circuits.
? semtech 2006 www.semtech.com 1-4 xe8806a/xe8807a 1.2 pin map the xe8806a and xe8807a can be delivered in different pack ages. the pin maps for the different packages are given below. 1.2.1 tqfp-32 1 pd(0) pa(0) vbat xout xin vss pa(7) pd(7) pb(2) pb(3) pd(3) pa(3) pa(4) pd(4) pb(4) pb(5) pb(6) pb(7) pd(5) pa(5) pa(6) pd(6) test vreg pb(1) pb(0) pd(2) pa(2) pa(1) pd(1) n reset vpp 17 9 25 figure 1-2. tqfp-32 pin map 1.2.2 so-28 pa(1)/pd(1) n reset vpp pd(0) pa(0) vbat xout xin vss pa(7) pd(7) vreg test pa(6)/pd(6) pd(2)/pa(2) pb(0) pb(1) pb(2) pb(3) pd(3) pa(3) pa(4) pd(4) pb(4) pb(5) pb(6) pb(7) pd(5)/pa(5) 15 28 14 1 figure 1-3. so28 pin map in the so-28 package, 4 pins of port a and port d are connected together. it is up to the user to choose between the functionality of port a or port d for these pins. note: if one of the pins pd(1), pd(2), pd(5), pd(6) is used as output, the pull up of the corresponding pin of port a should be disabled in order to have low power consumption.
? semtech 2006 www.semtech.com 1-5 xe8806a/xe8807a 1.2.3 so-24 pa(1)/pd(1) n reset vpp pa(0)/pd(0) vbat xout xin vss pa(7)/pd(7) vreg test pa(6)/pd(6) pd(2)/pa(2) pb(0) pb(1) pb(2) pb(3) pd(3)/pa(3) pd(4)/pa(4) pb(4) pb(5) pb(6) pb(7) pd(5)/pa(5) 13 24 12 1 figure 1-4. so24 pin map in the so-24 package, all pins of port a and port d ar e connected together. it is up to the user to choose between the functionality of port a or port d. note: if one of the pins of port d is used as outpu t, the pull up of the corresponding pin of port a should be disabled in order to have low power consumption.
? semtech 2006 www.semtech.com 1-6 xe8806a/xe8807a 1.2.4 bare die xe8806a the circuit is also available in bare die for chip on board assembly. all vbat pins and all vss pins should be connected together. the substrate of the circuit is connected to vss. (123, 3236) pb(6) (123,2970) vbat (123, 2658) pb(7) (123,2345) pd(5) (123,2113) pa(5) (123,1386) pa(6) (123,1072) pd(6) (123, 835) test (123, 545) vss (123, 310) vreg 4050m 3850m vss (3589,118) pd(0) (3324,118) pa(0) (3022,118) vbat (2808,118) xout (2572,118) xin (2141,118) vss (1906,118) vbat (1212,118) vbat ( 992,118) pa(7) ( 707,118) pd(7) ( 472,118) (3584,3580) pb(2) (3287,3580) pb(3) (2780,3580) pd(3) (2478,3580) pa(3) (1584,3580) pa(4) (1369,3580) pd(4) (1065,3580) vss ( 792,3580) pb(4) ( 477,3580) pb(5) pb(1) (3787,3078) pb(0) (3787,2714) pd(2) (3787,2354) pa(2) (3787,2082) pa(1) (3787,1530) pd(1) (3787,1178) nreset (3787, 913) vss (3787, 588) vpp (3787, 340) xemics figure 1-5. die dimension and pin location of the xe8806a
? semtech 2006 www.semtech.com 1-7 xe8806a/xe8807a 1.2.5 bare die xe8807a the circuit is also available in bare die for chip on board assembly. all vbat pins and all vss pins should be connected together. the substrate of the circuit is connected to vss. (123, 3236) pb(6) (123,2970) vbat (123, 2658) pb(7) (123,2345) pd(5) (123,2113) pa(5) (123,1386) pa(6) (123,1072) pd(6) (123, 835) test (123, 545) vss (123, 310) vreg 4050m 3850m vss (3589,118) pd(0) (3324,118) pa(0) (3022,118) vbat (2808,118) xout (2572,118) xin (2141,118) vss (1906,118) vss (1212,118) vbat ( 992,118) pa(7) ( 707,118) pd(7) ( 472,118) (3584,3580) pb(2) (3287,3580) pb(3) (2780,3580) pd(3) (2478,3580) pa(3) (1584,3580) pa(4) (1369,3580) pd(4) (1065,3580) vss ( 792,3580) pb(4) ( 477,3580) pb(5) pb(1) (3787,3078) pb(0) (3787,2714) pd(2) (3787,2354) pa(2) (3787,2082) pa(1) (3787,1530) pd(1) (3787,1178) nreset (3787, 913) vss (3787, 588) vpp (3787, 340) xemics figure 1-6. die dimension and pin location of the xe8807a 1.3 pin assignment the table below gives a short descripti on of the different pin assignments. pin assignment vbat positive power supply vss negative power supply vreg connection for the mandatory external capacitor of the voltage regulator vpp high voltage supply for flash memory programming (nc in rom versions) nreset resets the circuit when the voltage is low test sets the pin to flash programming mode xin/xout quartz crystal connections, al so used for flash memory programming pa(7:0) parallel input port a pins pb(7:0) parallel i/o port b pins pd(7:0) parallel i/o port d pins table 1-1. pin assignment
? semtech 2006 www.semtech.com 1-8 xe8806a/xe8807a table 1-2 gives a more detailed pin map for the different pins in the different packages. it also indicates the possible i/o configuration of these pins. the indications in blue bold are the configurat ion at start-up. please note that in the so-28 and so-24 package several functions are routed to the same package pins. these pins are indicated in red italic. the pins rfif(3:0) are the i/o pins of the rf interface, the cntx pins are possible counter inputs, pwmx are possible pwm outputs, t he cmpd pins are comparator inputs. pin number function i/o configuration tqfp-32 so-28 so-24 first second third ai ao di do od pu pd snap power 1 4 4 pd(7) x x x x 2 5 4 pa(7) x x x 3 6 5 vss x 4 7 6 xin x 5 8 7 xout x 6 9 8 vbat x 7 10 9 pa(0) cnta x x x 8 11 9 pd(0) rfif(0) x x x x 9 12 10 vpp x 10 13 11 nreset x x 11 14 12 pd(1) rfif(1) x x x x 12 14 12 pa(1) cntb x x x 13 15 13 pa(2) cntc x x x 14 15 13 pd(2) rfif(2) x x x x 15 16 14 pb(0) pwm0 x x x x x x 16 17 15 pb(1) pwm1 x x x x x x 17 18 16 pb(2) x x x x x x 18 19 17 pb(3) x x x x x x 19 20 18 pd(3) rfif(3) x x x x 20 21 18 pa(3) cntd x x x 21 22 19 pa(4) x x x 22 23 19 pd(4) x x x x 23 24 20 pb(4) usrt_s0 cmpd(0) x x x x x x 24 25 21 pb(5) usrt_s1 cmpd(1) x x x x x x 25 26 22 pb(6) uart_tx cmpd(2) x x x x x x 26 27 23 pb(7) uart_rx cmpd(3) x x x x x x 27 28 24 pd(5) x x x x 28 28 24 pa(5) x x x 29 1 1 pa(6) x x x 30 1 1 pd(6) x x x x 31 2 2 test x x 32 3 3 vreg x table 1-2. pin description table pin map table legend: red italic: pin shared with another peripheral in a specific package blue bold: configuration at start up ai: analog input ao: analog output di: digital input do: digital output od: nmos open drain output pu: pull-up resistor pd: pull-down resistor snap: snap-to-rail function (see peripheral description for detailed description) power: power supply
? semtech 2006 www.semtech.com 2-1 xe8806a/xe8807a 2 xe8806a and xe8807a performance 2.1 absolute maximum ratings 2-2 2.2 operating range 2-2 2.3 current consumption 2-3 2.4 operating speed 2-4 2.4.1 flash circuit version xe8806am 2-4 2.4.2 flash circuit version xe8807am 2-5 2.4.3 rom circuit version, regulator on 2-5 2.4.4 rom circuit version, regulator by-passed 2-6
? semtech 2006 www.semtech.com 2-2 xe8806a/xe8807a 2.1 absolute maximum ratings min. max. note voltage applied to vbat with respect to vss -0.3 6.0 v voltage applied to vpp with respect to vss vbat-0.3 12 v voltage applied to all pins except vpp and vbat vss-0.3 vbat+0.3 v storage temperature (rom device or unprogrammed flash device) -55 150 c storage temperature (programmed flash device) -40 85 c table 2-1. absolute maximal ratings stresses beyond the absolute maximal ratings may caus e permanent damage to the device. functional operation at the absolute maximal ratings is not implied. expos ure to conditions beyond the absolute maximal ratings may affect the reliability of the device. 2.2 operating range min. max. note voltage applied to vbat with respect to vss 2.4 5.5 v voltage applied to vbat with respect to vss during the flash programming 4.5 5.5 v 1 voltage applied to vpp with respect to vss vbat 11.5 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 85 c capacitor on vreg 0.8 1.2 f table 2-2. operating range for the flash device note 1. during the programming of the device, the supply voltage s hould at least be equal to t he supply voltage used during normal operation, and temperat ure between 10c and 40c. min. max. note vreg by-passed 1.2 5.5 v voltage applied to vbat with respect to vss vreg on 1.5 3.6 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 125 c capacitor on vreg 0.1 1.2 f 1 table 2-3. operating range for the rom device note 1. the capacitor may be omi tted when vreg is connected to vbat. all specifications in this document are valid for the complete operating range unless otherwise specified. min. max. note retention time at 85c 10 years 1 retention time at 55c 100 years 1 number of programming cycles 10 2 table 2-4. operating range of the flash memory note 1. valid only if programmed usi ng a programming tool that is qualified note 2. circuits can be programmed more than 10 times but in that case, the retention time is no longer guaranteed.
? semtech 2006 www.semtech.com 2-3 xe8806a/xe8807a 2.3 current consumption the tables below give the current consum ption for the circuit in different conf igurations. the figures are indicative only and may change as a function of the act ual software implemented in the circuit. table 2-5 gives the current consumption for the flash ve rsion of the circuit. the peripherals (usrt, uart, cnt, vld, cmpd) are disabled. the parallel ports are configur ed in input with pull up. their pins are not connected externally. operation mode cpu rc xtal consumption comments note high speed cpu 1 mips 1 mhz off 200 a 2.4v<>5.5v, 27 c 1 320 a 2 410 a 3 310 a 4 low speed cpu .1 mips 100 khz off 21 a 2.4v <>5.5v, 27 c 1 33 a 2 42 a 3 low power cpu 32 kips off 32 khz 7.5 a 2.4v <>5.5v, 27 c 1 11.0 a 2 14.5 a 3 low power time keeping halt off 32 khz 1.9 a 2.4v <>5.5v, 27 c fast wake-up time keeping halt ready 32khz 2.3 a 2.4v <>5.5v, 27 c immediate wake- up time keeping halt 1 mhz off 35 a 2.4v <>5.5v, 27 c vld static current 15 a 2.4v <>5.5v, 27 c cmpd static current 2 a 2.4v <>5.5v, 27 c table 2-5. typical current consum ption of the xe8806am version (8k in structions flash memory) and xe8807am version (4k instructions flash memory) 1. software without data access 2. 100% low power ram access 3. 100% ram access 4. typical software table 2-6 shows the typical current c onsumption for the rom version with 8k instructions. two possible modes are possible: a 2.4v-5.5v operating range using the internal regulator and a 1.2v-3.3v operating range short circuiting the voltage regulator (i.e. connect vreg to vbat). operation mode cpu rc xtal consumption comments note high speed cpu 1 mips 1 mhz off 200 2.4v<>5.5v, 27 c 1,2 max. speed cpu 4 mips 4 mhz off 800 2.4v<>5.5v, 27 c 1,2 low speed cpu .1 mips 100 khz off 21 2.4v <>5.5v, 27 c 1,2 low power cpu 32 kips off 32 khz 7 2.4v <>5.5v, 27 c 1,2 low voltage cpu 32 kips off 32 khz 1 1.2v, 27 c 1,3 low power time keeping halt off 32 khz 1.3 2.4v <>5.5v, 27 c 2 table 2-6. current consumption of the xe 8806ar version (8k instructions rom memory) 1. software using move instruction using in ternal cpu registers and peripheral registers. 2. using the internal voltage regulator (see figure 2-5). 3. with the internal regulator short circuited (i.e. by connecting vreg to vbat, see fi gure 2-7). in this case, the current consumption will increase with vbat.
? semtech 2006 www.semtech.com 2-4 xe8806a/xe8807a hints for low power operation: 1. use the low power ram instead of the ram for a ll parameters that are accessed frequently. the average current consumption for the low power ram is about 40 times lower than for the ram. 2. rather than using the circuit at low speed, it is bette r to use the circuit at higher speed and switch off the blocks when not needed. 3. the power consumption of the program memory is an im portant part of the overall pow er consumption. in case you intend to use a rom version and power consumption is too high, please ask us to provide you with a circuit version with smaller rom size. 2.4 operating speed 2.4.1 flash circuit version xe8806am the speed of the flash devices is not highly dependent upon the supply voltage. however, by limiting the temperature range, the speed can be increased. the mini mal guaranteed speed as a function of the supply voltage and maximal temperature operating temperature is given in figure 2-2. vbat vreg vss 2.4 - 5.5 v 1uf figure 2-1. supply configurati on for flash circuit operation. 0 0.5 1 1.5 2 2.5 3 3.5 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c figure 2-2. guaranteed speed as a function of the supply voltage and maximal temperature. note that the speed of the flash circuit version is limit ed by the flash memory. all ot her peripherals of the device can run at the same speed as the rom version (see fi gure 2-6). the maximal speed of the peripherals can be exploited by reducing the cpu frequency by a factor of 2 with respect to the clock source by executing the instruction ?freq div2?. take care to execute this in struction before increasing t he clock speed above the figures given in figure 2-2.
? semtech 2006 www.semtech.com 2-5 xe8806a/xe8807a 2.4.2 flash circuit version xe8807am the speed of the flash devices is not highly dependent upon the supply voltage. however, by limiting the temperature range, the speed can be increased. the mini mal guaranteed speed as a function of the supply voltage and maximal temperature operating temperature is given in figure 2-4. vbat vreg vss 2.4 - 5.5 v 1uf figure 2-3. supply configurati on for flash circuit operation. 0 1 2 3 4 5 6 7 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c figure 2-4. guaranteed speed as a function of the supply voltage and maximal temperature. 2.4.3 rom circuit version, regulator on for the rom version, two possible operating modes exis t: with and without voltage regulator. using the voltage regulator, a low power consumption will be obtained even with supply voltages above 2.4v. without the voltage regulator (i.e. vreg short-circuited to vbat) , a higher speed can be obtained. vbat vreg vss 2.4 - 5.5 v 100nf figure 2-5. supply configuration for rom circ uit operation using the internal regulator.
? semtech 2006 www.semtech.com 2-6 xe8806a/xe8807a 0 2 4 6 8 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-6. guaranteed speed as a function of supply volt age and for different maximal temperatures using the voltage regulator. 2.4.4 rom circuit version, regulator by-passed vbat vreg vss 1.2 ? 3.3 v figure 2-7. supply configuration for rom circui t operation by-passing the internal regulator. 0 2 4 6 8 1 1.5 2 2.5 3 3.5 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-8. guaranteed speed as a function of supply voltage and for two temperat ure ranges when vreg=vbat.
? semtech 2006 www.semtech.com 3-1 xe8806a/xe88l7a 3. cpu contents 3.1 cpu description 3-2 3.2 cpu internal registers 3-2 3.3 cpu instruction short reference 3-4
? semtech 2006 www.semtech.com 3-2 xe8806a/xe8807a 3.1 cpu description the cpu of the xe8000 series is a low power risc core. it has 16 internal registers for efficient implementation of the c compiler. its instruction set is made up of 35 gener ic instructions, all coded on 22 bits, with 8 addressing modes. all instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. the circuit therefore runs on 1 mips on a 1mhz clock. the cpu hardware and software description is given in the document ?coolrisc816 hardware and software reference manual?. a short summary is given in the following paragraphs. the good code efficiency of the cpu core make s it possible to compute a polynomial like y b b x y a a z ? + + ? ? + = 1 0 1 0 ) ( in less than 300 clock cycles (software code generated by the xemics c- compiler, all numbers are signed integers on 16 bits). 3.2 cpu internal registers as shown in figure 3-1, the cpu has 16 internal 8-bit r egisters. some of these regi sters can be concatenated to a 16-bit word for use in some instructions. the function of t hese registers is defined in tabl e 3-1. the status register stat (table 3-2) is used to manage the different interrupt and event levels. an interrupt or an event can both be used to wake up after a halt instruction. the difference is that an interrupt jumps to a special interrupt function whereas an event continues the softwar e execution with the instruction following the halt instruction. the program counter (pc) is a 16 bit r egister that indicates the address of t he instruction that has to be executed. the stack (st n ) is used to memorise the return address when executing subroutines or interrupt routines. instruction memory 22bit cpu cpu internal registers a stat iph ipl i3h i3l i2h i2l i1h i1l i0h i0l r3 r2 r1 r0 data memory data bus instruction bus pc st 1 st 2 st 3 st 4 program counter stack figure 3-1. cpu internal registers
? semtech 2006 www.semtech.com 3-3 xe8806a/xe8807a register name register function r0 general purpose r1 general purpose r2 general purpose r3 data memory offset i0h msb of the data memory index i0 i0l lbs of the data memory index i0 i1h msb of the data memory index i1 i1l lbs of the data memory index i1 i2h msb of the data memory index i2 i2l lbs of the data memory index i2 i3h msb of the data memory index i3 i3l lbs of the data memory index i3 iph msb of the program memory index ip ipl lbs of the program memory index ip stat status register a accumulator table 3-1. cpu internal register definition bit name function 7 ie2 enables (when 1) the interrupt request of level 2 6 ie1 enables (when 1) the interrupt request of level 1 5 gie enables (when 1) all interrupt request levels 4 in2 interrupt request of level 2. the interr upts labelled ?low? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 3 in1 interrupt request of level 1. the interr upts labelled ?mid? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 2 in0 interrupt request of level 0. the interr upts labelled ?hig? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 1 ev1 event request of level 1. the events labe lled ?low? in the event handler are routed to this event level. this bit has to be cleared when the event is served. 0 ev0 event request of level 1. the events labe lled ?hig? in the event handler are routed to this event level. this bit has to be cleared when the event is served. table 3-2. status register description the cpu also has a number of flags that can be used for c onditional jumps. these flags are defined in table 3-3. symbol name function z zero z=1 when the accumulator a content is zero c carry this flag is used in sh ift or arithmetic operations. for a shift operation, it has the value of the bit that was shifted out (lsb for shift right, msb for shift left). for an arithmetic operation with unsigned numbers: it is 1 at occurrence of an overfl ow during an addition (or equivalent). it is 0 at occurrence of an underflow during a subtraction (or equivalent). v overflow this flag is used in shift or arithmetic operations. for arithmetic or shift operations with signed numbers, it is 1 if an overflow or underflow occurs. table 3-3. flag description
? semtech 2006 www.semtech.com 3-4 xe8806a/xe8807a 3.3 cpu instruction short reference table 3-4 shows a short description of the different in structions available on t he coolrisc816. the notation cc in the conditional jump instruction refers to the conditi on description as given in table 3-6. the notation reg, reg1, reg2, reg3 refers to one of the cpu internal registers of table 3-1. the notation eaddr and dm(eaddr) refer to one of the extended address modes as defined in tabl e 3-5. the notation dm(xxx) refers to the data memory location with address xxx. instruction modification operation jump addr[15:0] -,-,-, - pc := addr[15:0] jump ip -,-,-, - pc := ip j cc addr[15:0] -,-,-, - if cc is true then pc := addr[15:0] j cc ip -,-,-, - if cc is true then pc := ip call addr[15:0] -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := addr[15:0] call ip -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := ip calls addr[15:0] -,-,-, - ip := pc+1; pc := addr[15:0] calls ip -,-,-, - ip := pc+1; pc := ip ret -,-,-, - pc := st 1 ; st n := st n+1 (n>1) rets -,-,-, - pc := ip reti -,-,-, - pc := st 1 ; st n := st n+1 (n>1); gie :=1 push -,-,-, - pc := pc+1; st n+1 := st n (n>1); st 1 := ip pop -,-,-, - pc := pc+1; ip := st 1 ; st n := st n+1 (n>1) move reg ,#data[7:0] -,-, z, a a := data[7:0]; reg := data[7:0] move reg1 , reg2 -,-, z, a a := reg2 ; reg1 := reg2 move reg , eaddr -,-, z, a a := dm(eaddr) ; reg := dm(eaddr) move eaddr , reg -,-,-, - dm(eaddr) := reg move addr[7:0],#data[7:0] -,-,-, - dm(addr[7:0]) := data[7:0] cmvd reg1 , reg2 -,-, z, a a := reg2 ; if c=0 then reg1 := a; cmvd reg , eaddr -,-, z, a a := dm(eaddr) ; if c=0 then reg := a cmvs reg1 , reg2 -,-, z, a a := reg2 ; if c=1 then reg1 := a; cmvs reg , eaddr -,-, z, a a := dm(eaddr) ; if c=1 then reg := a shl reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := 0; c := reg2[7] ; reg1 := a shl reg c, v, z, a a := reg <<1; a[0] := 0; c := reg[7] ; reg := a shl reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] ; reg := a shlc reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := c; c := reg2[7] ; reg1 := a shlc reg c, v, z, a a := reg <<1; a[0] := c; c := reg[7] ; reg := a shlc reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] := c; c := dm(eaddr)[7] ; reg := a shr reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := 0; c := reg2[0] ; reg1 :=a shr reg c, v, z, a a := reg >>1; a[7] := 0; c := reg[0] ; reg := a shr reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := 0; c := dm(eaddr)[0] ; reg := a shrc reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := c; c := reg2[0] ; reg1 := a shrc reg c, v, z, a a := reg >>1; a[7] := c; c := reg[0] ; reg := a shrc reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := c; c := dm(eaddr)[0] ; reg := a shra reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := reg2[7] ; c := reg2[0] ; reg1 := a shra reg c, v, z, a a := reg >>1; a[7] := reg[7] ; c := reg[0] ; reg := a shra reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := dm(eaddr)[7] ; c := dm(eaddr)[0] ; reg := a cpl1 reg1 , reg2 -,-, z, a a := not( reg2 ); reg1 := a cpl1 reg -,-, z, a a := not( reg ); reg := a cpl1 reg , eaddr -,-, z, a a := not( dm(eaddr) ); reg := a cpl2 reg1 , reg2 c, v, z, a a := not( reg2 )+1; if a=0 then c:=1 else c := 0; reg1 := a cpl2 reg c, v, z, a a := not( reg )+1; if a=0 then c:=1 else c := 0; reg := a cpl2 reg , eaddr c, v, z, a a := not( dm(eaddr) )+1; if a=0 then c:=1 else c := 0; reg := a cpl2c reg1 , reg2 c, v, z, a a := not( reg2 )+c; if a=0 and c=1 then c:=1 else c := 0; reg1 := a cpl2c reg c, v, z, a a := not( reg )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a cpl2c reg , eaddr c, v, z, a a := not( dm(eaddr) )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a inc reg1 , reg2 c, v, z, a a := reg2 +1; if a=0 then c := 1 else c := 0; reg1 := a inc reg c, v, z, a a := reg +1; if a=0 then c := 1 else c := 0; reg := a inc reg , eaddr c, v, z, a a := dm(eaadr) +1; if a=0 then c := 1 else c := 0; reg := a incc reg1 , reg2 c, v, z, a a := reg2 +c; if a=0 and c=1 then c := 1 else c := 0; reg1 := a incc reg c, v, z, a a := reg +c; if a=0 and c=1 then c := 1 else c := 0; reg := a incc reg , eaddr c, v, z, a a := dm(eaadr) +c; if a=0 and c=1 then c := 1 else c := 0; reg := a dec reg1 , reg2 c, v, z, a a := reg2 -1; if a=hff then c := 0 else c := 1; reg1 := a
? semtech 2006 www.semtech.com 3-5 xe8806a/xe8807a dec reg c, v, z, a a := reg -1; if a=hff then c := 0 else c := 1; reg := a dec reg , eaddr c, v, z, a a := dm(eaddr) -1; if a=hff then c := 0 else c := 1; reg := a decc reg1 , reg2 c, v, z, a a := reg2 -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg1 := a decc reg c, v, z, a a := reg -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a decc reg , eaddr c, v, z, a a := dm(eaddr) -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a and reg ,#data[7:0] -,-, z, a a := reg and data[7:0]; reg := a and reg1 , reg2 , reg3 -,-, z, a a := reg2 and reg3 ; reg1 := a and reg1 , reg2 -,-, z, a a := reg1 and reg2 ; reg1 := a and reg , eaddr -,-, z, a a := reg and dm(eaddr) ; reg := a or reg ,#data[7:0] -,-, z, a a := reg or data[7:0]; reg := a or reg1 , reg2 , reg3 -,-, z, a a := reg2 or reg3 ; reg1 := a or reg1 , reg2 -,-, z, a a := reg1 or reg2 ; reg1 := a or reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a xor reg ,#data[7:0] -,-, z, a a := reg xor data[7:0]; reg := a xor reg1 , reg2 , reg3 -,-, z, a a := reg2 xor reg3 ; reg1 := a xor reg1 , reg2 -,-, z, a a := reg1 xor reg2 ; reg1 := a xor reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a add reg ,#data[7:0] c, v, z, a a := reg +data[7:0]; if overflow then c:=1 else c := 0; reg := a add reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 ; if overflow then c:=1 else c := 0; reg1 := a add reg1 , reg2 c, v, z, a a := reg1 + reg2 ; if overflow then c:=1 else c := 0; reg1 := a add reg , eaddr c, v, z, a a := reg + dm(eaddr) ; if overflow then c:=1 else c := 0; reg := a addc reg ,#data[7:0] c, v, z, a a := reg +data[7:0]+c; if overflow then c:=1 else c := 0; reg := a addc reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg1 , reg2 c, v, z, a a := reg1 + reg2 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg , eaddr c, v, z, a a := reg + dm(eaddr) +c; if overflow then c:=1 else c := 0; reg := a subd reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c := 0 else c := 1; reg := a subd reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 ; if underflow then c := 0 else c := 1; reg1 := a subd reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c := 0 else c := 1; reg1 := a subd reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c := 0 else c := 1; reg := a subdc reg ,#data[7:0] c, v, z, a a := data[7:0]- reg -(1-c); if underflow then c := 0 else c := 1; reg := a subdc reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg1 , reg2 c, v, z, a a := reg2 - reg1 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg , eaddr c, v, z, a a := dm(eaddr) - reg -(1-c); if underflow then c := 0 else c := 1; reg := a subs reg ,#data[7:0] c, v, z, a a := reg -data[7:0]; if underflow then c := 0 else c := 1; reg := a subs reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg1 , reg2 c, v, z, a a := reg1 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg , eaddr c, v, z, a a := reg - dm(eaddr) ; if underflow then c := 0 else c := 1; reg := a subsc reg ,#data[7:0] c, v, z, a a := reg -data[7:0]-(1-c); if underflow then c := 0 else c := 1; reg := a subsc reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg1 , reg2 c, v, z, a a := reg1 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg , eaddr c, v, z, a a := reg - dm(eaddr) -(1-c); if underflow then c := 0 else c := 1; reg := a mul reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mul reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mul reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mul reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mula reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mula reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mula reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mula reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mshl reg ,#shift[2:0] u, u, u, a a := ( reg *2 shift )[7:0]; reg := ( reg *2 shift )[15:8] mshr reg ,#shift[2:0] u, u, u, a a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] mshra reg ,#shift[2:0] u, u, u, a* a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] cmp reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) tstb reg ,#bit[2:0] -, -, z, a a[bit] := reg[bit] ; other bits in a are 0 setb reg ,#bit[2:0] -, -, z, a reg[bit] := 1; other bits unchanged; a := reg clrb reg ,#bit[2:0] -, -, z, a reg[bit] := 0; other bits unchanged; a := reg invb reg ,#bit[2:0] -, -, z, a reg[bit] := not reg[bit] ; other bits unchanged; a := reg
? semtech 2006 www.semtech.com 3-6 xe8806a/xe8807a sflag -,-,-, a a[7] := c; a[6] := c xor v; a[5] := st full; a[4] := st empty rflag reg c, v, z, a a := reg << 1; ; a[0] := 0; c := reg[7] rflag eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] freq divn -,-,-, - reduces the cpu fr equency (divn=nodiv, div2, div4, div8, div16) halt -,-,-, - halts the cpu nop -,-,-, - no operation - = unchanged, u = undefined, *mshr reg ,# 1 doesn?t shift by 1 table 3-4. instruction short reference the coolrisc816 has 8 different addressing modes. these modes are described in table 3-5. in this table, the notation ix refers to one of the data memory index registers i0, i1, i2 or i3. using eaddr in an instruction of table 3-4 will access the data memory at the address dm(eaddr) and will simultaneously exec ute the index operation. extended address eaddr accessed data memory location dm(eaddr) index operation addr[7:0] dm(h00&addr[7:0]) - direct addressing (ix) dm(ix) - indexed addressing (ix, offset[7:0]) dm(ix+offset) - indexed addressing with immediate offset (ix,r3) dm(ix+r3) - indexed addressing with register offset (ix)+ dm(ix) ix := ix+1 indexed addressing with index post-increment (ix,offset[7:0])+ dm(ix+offset) ix := ix+offset indexed addressing with index post-increment by the offset -(ix) dm(ix-1) ix := ix-1 indexed addressing with index pre-decrement -(ix,offset[7:0]) dm(ix-offset) ix := ix -offset indexed addressing with index pre-decrement by the offset table 3-5. extended address mode description eleven different jump conditions are implemented as shown in table 3-6. the contents of the column cc in this table should replace the cc notation in the instructi on description of table 3-4. cc condition cs c=1 cc c=0 zs z=1 zc z=0 vs v=1 vc v=0 ev (ev1 or ev0)=1 after cmp op1,op2 eq op1=op2 ne op1 op2 gt op1>op2 ge op1 op2 lt op1 ? semtech 2006 www.semtech.com 4-1 xe8806a/xe8807a 4. memory mapping 4.1 memory organisation 4-2 4.2 quick reference data memory register map 4-2 4.2.1 low power data registers (h0000-h0007) 4-3 4.2.2 system, clock configuration and reset configuration (h0010-h001f) 4-3 4.2.3 port a (h0020-h0027) 4-4 4.2.4 port b (h0028-h002f) 4-4 4.2.5 port d (h0030-h0033) 4-4 4.2.6 flash programming (h0038-003b) 4-4 4.2.7 event handler (h003c-h003f) 4-5 4.2.8 interrupt handler (h0040-h0047) 4-5 4.2.9 usrt (h0048-h004f) 4-6 4.2.10 uart (h0050-h0057) 4-6 4.2.11 counter/timer/pwm registers (h0058-h005f) 4-7 4.2.12 rf interface (h0060-h0067) 4-7 4.2.13 comparator registers (h0072-h0073) 4-7 4.2.14 voltage level detector registers (h007e-h007f) 4-8 4.2.15 ram (h0080-h027f) 4-8
? semtech 2006 www.semtech.com 4-2 xe8806a/xe8807a 4.1 memory organisation the xe8806a and xe8807a cpu are built wi th harvard architecture. the harvard architecture uses separate instruction and data memories. the instruction bus and data bus are also separated. the advantage of such a structure is that the cpu can fetch a new instruction and read/write data simu ltaneously. the circuit configuration is shown in figure 4-1. the cpu has its 16 internal regist ers. the instruction memory has a capacity of 8192 22-bit instructions in the xe8806a and 4096 22-bi t instructions in the xe8807a. the data memory space has 8 low power registers, the peripheral regist er space and 512 bytes of ram. figure 4-1. memory mapping the cpu internal registers are described in the cpu c hapter. a short reference of the low power registers and peripheral registers is given in 4.2. 4.2 quick reference data memory register map the data register map is given in the tables below. a more detailed description of the diffe rent registers is given in the detailed description of the different peripherals. the tables give the following information: 1. the register name and register address 2. the different bits in the register 3. the access mode of the different bits (see table 4-1 for code description) 4. the reset source and reset value of the different bits the reset source coding is given in table 4-2. to get a full description of the reset sources, please refer to the reset block chapter. 0h027f ram capacity: 512 bytes 0h0080 0h1fff instruction memory capacity: xe8806a 8k x 22bit xe8807a 4k x 22bit cpu cpu internal registers a stat iph ipl i3h i3l i2h i2l i1h i1l i0h i0l r3 r2 r1 r0 low power data registers 0h0000 0h007f peripheral registers 0h0008 data memory data bus instruction bus
? semtech 2006 www.semtech.com 4-3 xe8806a/xe8807a code access mode r bit can be read w bit can be written r0 bit always reads 0 r1 bit always reads 1 c bit is cleared by writing any value c1 bit is cleared by writing a 1 ca bit is cleared after reading s special function, verify the detailed description in the respective peripherals table 4-1. access mode codes used in the register definitions code reset source glob nresetglobal cold nresetcold pconf nresetpconf sleep nresetsleep table 4-2. reset source coding used in the register definitions 4.2.1 low power data registers (h0000-h0007) name address 7 6 5 4 3 2 1 0 reg00 h0000 reg00[7:0] rw,00000000,glob reg01 h0001 reg01[7:0] rw,00000000,glob reg02 h0002 reg02[7:0] rw,00000000,glob reg03 h0003 reg03[7:0] rw,00000000,glob reg04 h0004 reg04[7:0] rw,00000000,glob reg05 h0005 reg05[7:0] rw,00000000,glob reg06 h0006 reg06[7:0] rw,00000000,glob reg07 h0007 reg07[7:0] rw,0000000,glob table 4-3. low power data registers 4.2.2 system, clock configuration and reset configuration (h0010-h001f) name address 7 6 5 4 3 2 1 0 regsysctrl h0010 sleepen rw,0,cold enresetpconf rw,0,cold enbuserror rw,0,cold enresetwd rw,0,cold r0 r0 r0 r0 regsysreset h0011 sleep rw,0,glob sleepflag rc,0,cold resetbuserror rc, 0, cold resetwd rc, 0, cold resetfromporta rc, 0, cold r0 r0 r0 regsysclock h0012 cpusel rw,0,sleep r0 enextclock rw,0,cold biasrc rw,1,cold coldxtal r,1,sleep r0 enablextal rw,0,sleep enablerc rw,1,sleep regsysmisc h0013 r0 r0 r0 r0 r0 r0 output16k rw,0,sleep outputcpuck rw,0,sleep regsyswd h0014 r0 r0 r0 r0 watchdog[3:0] s,0000,glob regsyspre0 h0015 r0 r0 r0 r0 r0 r0 r0 clearlowpresca l c1r0,0,- regsysrctrim1 h001b r0 r0 r0 rcfreqrange rw,0,cold rcfreqcoarse[3:0] rw,0001,cold regsysrctrim2 h001c r0 r0 rcfreqfine[5:0] rw,00000,cold table 4-4. reset block and clock block registers
? semtech 2006 www.semtech.com 4-4 xe8806a/xe8807a 4.2.3 port a (h0020-h0027) name address 7 6 5 4 3 2 1 0 regpain h0020 pain[7:0] r regpadebounce h0021 padebounce[7:0] rw,00000000,pconf regpaedge h0022 paedge[7:0] rw,00000000,glob regpapullup h0023 papullup[7:0] rw,11111111,pconf regpares0 h0024 pares0[7:0] rw, 00000000, glob regpares1 h0025 pares1[7:0] rw,00000000,glob regpactrl h0026 r0 r0 r0 r0 r0 r0 r0 debfast rw,0,pconf regpasnaptorail h0027 pasnaptorail[7:0] rw,00000000,pconf table 4-5. port a registers 4.2.4 port b (h0028-h002f) name address 7 6 5 4 3 2 1 0 regpbout h0028 pbout[7:0] rw,00000000,pconf regpbin h0029 pbin[7:0] r regpbdir h002a pbdir[7:0] rw,00000000,pconf regpbopen h002b pbopen[7:0] rw,00000000,pconf regpbpullup h002c pbpullup[7:0] rw,11111111,pconf regpbana h002d pbana[7:0] rw,00000000,pconf table 4-6. port b registers 4.2.5 port d (h0030-h0033) name address 7 6 5 4 3 2 1 0 regpdout h0030 pdout[7:0] rw,00000000,pconf regpdin h0031 pdin[7:0] r regpddir h0032 pddir[7:0] rw,00000000,pconf regpdpullup h0033 pdsnaptorail[3:0] rw,0000,pconf pdpullup[3:0] rw,1111,pconf table 4-7. port d registers 4.2.6 flash programming (h0038-003b) these four registers are used during flash programmi ng only. refer to the flash programming algorithm documentation for more details.
? semtech 2006 www.semtech.com 4-5 xe8806a/xe8807a 4.2.7 event handler (h003c-h003f) name address 7 6 5 4 3 2 1 0 regevn h003c cntirqa rc1,0,glob cntirqc rc1,0,glob 128hz rc1,0,glob paevn[1] rc1,0,glob cntirqb rc1,0,glob cntirqd rc1,0,glob 1hz rc1,0,glob paevn[0] rc1,0,glob regevnen h003d evnen[7:0] rw,00000000,glob regevnpriority h003e evnpriority[7:0] r,11111111,glob regevnevn h003f r0 r0 r0 r0 r0 r0 evnhigh r,0,glob evnlow r,0,glob table 4-8. event handler registers the origin of the different events is summarised in the table below. event event source cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) paevn[1:0] port a table 4-9. event source description 4.2.8 interrupt handler (h0040-h0047) name address 7 6 5 4 3 2 1 0 regirqhig h0040 rfifrx rc1,0,glob 128hz rc1,0,glob rfiftx rc1,0,glob cntirqa rc1,0,glob cntirqc rc1,0,glob cmpdirq rc1,0,glob uartirqtx rc1,0,glob uartirqrx rc1,0,glob regirqmid h0041 usrtcond2 rc1,0,glob urstcond1 rc1,0,glob pairq[5] rc1,0,glob pairq[4] rc1,0,glob 1hz rc1,0,glob vldirq rc1,0,glob pairq[1] rc1,0,glob pairq[0] rc1,0,glob regirqlow h0042 pairq[7] rc1,0,glob pairq[6] rc1,0,glob cntirqb rc1,0,glob cntirqd rc1,0,glob pairq[3] rc1,0,glob pairq[2] rc1,0,glob r0 r0 regirqenhig h0043 irqenhig[7:0] rw,0000000,glob regirqenmid h0044 irqenmid[7:0] rw,0000000,glob regirqenlow h0045 irqenlow[7:0] rw,0000000,glob regirqpriority h0046 irqpriority[7:0] r,11111111,glob regirqirq h0047 r0 r0 r0 r0 r0 irqhig r,0,glob irqmid r,0,glob irqlow r,0,glob table 4-10. interrupt handler registers the origin of the different interrupts is summarised in the table below.
? semtech 2006 www.semtech.com 4-6 xe8806a/xe8807a interrupt interrupt source cmpdirq low power comparators cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) pairq[7:0] port a rfifrx rf interface reception rfiftx rf interface transmission uartirqrx uart reception uartirqtx uart transmission usrtcond1 usrt condition 1 usrtcond2 usrt condition 2 vldirq voltage level detector table 4-11. interrupt source description 4.2.9 usrt (h0048-h004f) name address 7 6 5 4 3 2 1 0 regusrts1 h0048 r0 r0 r0 r0 r0 r0 r0 usrts1 s,1,glob regusrts0 h0049 r0 r0 r0 r0 r0 r0 r0 usrts0 s,1,glob regusrtcond1 h004a r0 r0 r0 r0 r0 r0 r0 usrtcond1 rc,0,glob regusrtcond2 h004b r0 r0 r0 r0 r0 r0 r0 usrtcond2 rc,0,glob regusrtctrl h004c r0 r0 r0 r0 usrtwaits0 r,0,glob usrtenwaitcond1 rw,0,glob usrtenwaits0 rw,0,glob usrtenable rw,0,glob regusrtbuffers1 h004d r0 r0 r0 r0 r0 r0 r0 usrtbuffers1 r,0,glob regusrtedges0 h004e r0 r0 r0 r0 r0 r0 r0 usrtedges0 r,0,glob table 4-12. usrt register description 4.2.10 uart (h0050-h0057) name address 7 6 5 4 3 2 1 0 reguartctrl h0050 uartecho rw,0,glob uartenrx rw,0,glob uartentx rw,0,glob uartxrx rw,0,glob uartxtx rw,0,glob uartbr[2:0] rw,101,glob reguartcmd h0051 selxtal rw,0,glob r0 uartrcsel[2:0] rw,000,glob uartpm rw,0,glob uartpe rw,0,glob uartwl rw,1,glob reguarttx h0052 uarttx[7:0] rw,0000000,glob reguarttxsta h0053 r0 r0 r0 r0 r0 r0 uarttxbusy r,0,glob uarttxfull r,0,glob reguartrx h0054 uartrx[7:0] r,00000000,glob reguartrxsta h0055 r0 r0 uartrxserr r,0,glob uartrxperr r,0,glob uartrxferr r,0,glob uartrxoerr rc,0,glob uartrxbusy r,0,glob uartrxfull r,0,glob table 4-13. uart register description
? semtech 2006 www.semtech.com 4-7 xe8806a/xe8807a 4.2.11 counter/timer/pwm registers (h0058-h005f) name address 7 6 5 4 3 2 1 0 regcnta h0058 countera[7:0] s,00000000,glob regcntb h0059 counterb[7:0] s,00000000,glob regcntc h005a counterc[7:0] s,00000000,glob regcntd h005b counterd[7:0] s,00000000,glob regcntctrlck h005c cntdcksel[1:0] rw,00,glob cntccksel[1:0] rw,00,glob cntbcksel[1:0] rw,00,glob cntacksel[1:0] rw,00,glob regcntconfig1 h005d cntddownup rw,0,glob cntcdownup rw,0,glob cntbdownup rw,0,glob cntadownup rw,0,glob cascadecd rw,0,glob cascadeab rw,0,glob cntpwm1 rw,0,glob cntpwm0 rw,0,glob regcntconfig2 h005e capsel[1:0] rw,00,glob capfunc[1:0] rw,00,glob pwm1size[1:0] rw,00,glob pwm0size[1:0] rw,00,glob regcnton h005f cntdextdiv rw,0,glob cntcextdiv rw,0,glob cntbextdiv rw,0,glob cntaextdiv rw,0,glob cntdenable rw,0,glob cntcenable rw,0,glob cntbenable rw,0,glob cntaenable rw,0,glob table 4-14. counter/timer/pwm register description. 4.2.12 rf interface bitjockey (h0060-h0067) name address 7 6 5 4 3 2 1 0 regrfifcmd1 h0060 r0 r0 rfifbrcoarse[1:0] rw,00,glob rfifbrfine[3:0] rw,0000,glob regrfifcmd2 h0061 rfifenstart[1:0] rw,00,glob rfifencod rw,0,glob rfifrxclock rw,0,glob rfiftxclock rw,0,glob rfifpcm[2:0] rw,000,glob regrfifcmd3 h0062 rfifrxirqen[2:0] rw,000,glob rfifrxirqmem[2:0] rc1,000,glob rfifenrx rw,0,conf rfifentx rw,0,conf regrfiftx h0063 rfiftx wr0,00000000,glob regrfiftxsta h0064 r0 r0 r0 r0 rfiftxfifooverrun rc1,0,glob rfiftxfifofull r,0,glob rfiftxfifoempty r,1,glob rfiftxstopped r,0,glob regrfifrx h0065 rfifrx r,00000000,glob regrfifrxsta h0066 r0 r0 r0 rfifrxfifooverrun rc1,0,glob rfifrxfifofull r,0,glob rfifrxstartdet rc1,0,glob rfifrxbusy r,0,glob rfifrxready r,0,glob regrfifspat h0067 rfifspat[7:0] rw,0000000,glob table 4-15. rf interface (rfif) register description. 4.2.13 comparator registers (h0072-h0073) name address 7 6 5 4 3 2 1 0 regcmpdstat h0072 cmpdstat[3:0] rca,0000,glob cmpdout[3:0] r,0000,glob regcmpdctrl h0073 irqonrising[2:0] rw,000,glob enirqch[3:0] rw,0000,glob enable rw,0,glob table 4-16. low power comparator registers
? semtech 2006 www.semtech.com 4-8 xe8806a/xe8807a 4.2.14 voltage level detector registers (h007e-h007f) name address 7 6 5 4 3 2 1 0 regvldctrl h007e r0 r0 r0 r0 vldrange rw,0,glob vldtune[2:0] rw,000,glob regvldstat h007f r0 r0 r0 r0 r0 vldresult r,0,glob vldvalid r,0,glob vlden rw,0,glob table 4-17. voltage level detector register description 4.2.15 ram (h0080-h027f) the 512 ram bytes can be accessed for read and write oper ations. the ram has no reset function. variables stored in the ram should be initialised before use sinc e they can have any value at circuit start up.
? semtech 2006 www.semtech.com 5-1 xe8806a/xe8807a 5. low power modes 5.1 feat ures ................................................................................................................... ............... 5-2 5.1.1 ov erview ................................................................................................................. ................ 5-2 5.2 operat ing mode ............................................................................................................. ......... 5-2
? semtech 2006 www.semtech.com 5-2 xe8806a/xe8807a 5.1 features 5.1.1 overview the xe8000 chips have three operating modes. these are the normal, low current and very low current modes (see figure 5-1). the different modes are controlled by the reset and clock blocks (s ee the documentation of the respective blocks). 5.2 operating mode start-up all bits are reset in the design when a por or padnreset is active. rc is enabled, xtal is disabled and cpu is reset (pmaddr = 0000). if the port a is used to return from the sleep mode, all bits with nresetcold do not change (see sleep mode) start-up all bits with nresetglobal and nresetpconf(if enabled) are reset. clock configuration doesn?t change except cpuck (freqdiv is reset, see clock block). cpu is reset active mode this is the mode where the cpu and all periphera ls can work and execute the embedded software. standby mode executing a halt instruction moves the xe8000 into t he standby mode. the cpu is stopped, but the clocks remain active. therefore, the enabled peripherals remain ac tive e.g. for time keeping. a reset or an interrupt/event request (if enabled) cancels the standby mode. sleep mode this is a very low-power mode because all circuit cloc ks and all peripherals are stopped. only some service blocks remain active. no time-keeping is possible. two instru ctions are necessary to move into sleep mode. first, the sleepen (sleep enable) bit in regsysctrl has to be set to 1. the sleep mode can then be activated by setting the sleep bit in regsysreset to 1. there are three possibe ways to wake-up from the sleep mode: 1. the por (power-on-reset caus ed by a power-down followed by pow er-on). the ram information is lost. 2. the padnreset 3. the port a reset combination (if the port a is present in the product). s ee port a documentation for more details. note : if the port a is used to return from the sleep mode, all bits with nresetcold do not change ( regsysctrl , regsysreset (except bit sleep ), enextclock and biasrc in regsysclock , regsysrctrim1 and regsysrctrim2 ). the sleepflag bit in regsysreset , reads back a 1 if the circuit was in sleep mode since the flag was last cleared (see reset block for more details). note : it is recommended to insert a nop instruction after t he instruction that sets the circuit in sleep mode because this instruction can be executed when the sleep mode is left using the resetfromporta.
? semtech 2006 www.semtech.com 5-3 xe8806a/xe8807a start-up reset active stand-by sleep halt instruction interrupt/event set bit sleep por padnreset porta reset por padnreset normal mode low current very low current por padnreset porta reset watchdog reset buserror reset porta reset watchdog reset por padnreset without condition without condition figure 5-1. xe8000 operating modes.
? semtech 2006 www.semtech.com 6-1 xe8806a/xe8807a 6. reset generator 6.1 features 6-2 6.2 overview 6-2 6.3 register map 6-2 6.4 reset handling capabilities 6-3 6.5 reset source description 6-4 6.5.1 power on reset 6-4 6.5.2 nreset pin 6-4 6.5.3 programmable port a input combination 6-4 6.5.4 watchdog reset 6-4 6.5.5 buserror reset 6-5 6.6 sleep mode 6-5 6.7 control register description and operation 6-5 6.8 watchdog 6-5 6.9 start-up and watchdog specifications 6-6
? semtech 2006 www.semtech.com 6-2 xe8806a/xe8807a 6.1 features ? power on reset (por) ? external reset from the nreset pin ? programmable watchdog timer reset ? programmable buserror reset ? sleep mode management product dependant: ? programmable port a input combination reset 6.2 overview the reset block is the reset manager. it handles the di fferent reset sources and distributes them through the system. it also controls the sleep mode of the circuit. 6.3 register map register name regsysctrl regsysreset regsyswd table 6-1. reset registers table 6-1 gives the different r egisters used by this block.
? semtech 2006 www.semtech.com 6-3 xe8806a/xe8807a pos. regsysctrl rw reset function 7 sleepen r w 0 nresetcold enables sleep mode 0: sleep mode is disabled 1: sleep mode is enabled 6 enresetpconf r w 0 nresetcold enables the nresetpconf signal when the nresetglobal is active 0: nresetpconf is disabled 1: nresetpconf is enabled 5 enbuserror r w 0 nresetcold enables reset from buserror 0: buserror reset source is disabled 1: buserror reset source is enabled 4 enresetwd r w 0 nresetcold enables reset from watchdog 0: watchdog reset source is disabled 1: watchdog reset source is enabled this bit can not be set to 0 by sw 3 ? 0 - r 0000 unused table 6-2. regsysctrl register. pos. regsysreset rw reset function 7 sleep rw 0 nresetglobal sleep mode control (reads always 0) 6 sleepflag r c 0 nresetcold sleep mode was active before 5 resetbuserror r c 0 nresetcold reset source was buserror 4 resetwd r c 0 nresetcold reset source was watchdog 3 resetfromporta r c 0 nresetcold reset source was port a combination 2 ? 0 r 000 unused table 6-3. regsysreset register pos. regsyswd rw reset function 7 - 4 - r 0000 unused wdkey[3] w watchdog key bit 3 3 wdcounter[3] r 0 nresetglobal watchdog counter bit 3 wdkey[2] w watchdog key bit 2 2 wdcounter[2] r 0 nresetglobal watchdog counter bit 2 wdkey[1] w watchdog key bit 1 1 wdcounter[1] r 0 nresetglobal watchdog counter bit 1 wdkey[0] w watchdog key bit 0 0 wdcounter[0] r 0 nresetglobal watchdog counter bit 0 table 6-4. regsyswd register 6.4 reset handling capabilities there are 5 reset sources: ? power on reset (por) ? external reset from the nreset pin ? programmable port a input combination ? programmable watchdog timer reset ? programmable buserror reset on processor access outside the allocated memory map
? semtech 2006 www.semtech.com 6-4 xe8806a/xe8807a another reset source is the bit sleep in the regsysreset register. this source is fully controlled by software and is only used during the sleep mode. four internal reset signals are generated from these sources and distri buted through the system: ? nresetcold: is asserted on por or by the nreset pin ? nresetglobal: is asserted when nresetcold or any other enabled reset source is active ? nresetsleep: is asserted w hen the circuit is in sleep mode ? nresetpconf: is asserted when nresetglobal is active and if the enresetpconf bit in the regsysctrl register is set. this reset is generally used in the differ ent ports. it allows to maintain the port configuration unchanged while the rest of the circuit is reset. table 6-5 shows a summary of the dependency of the inte rnal reset signals on the various reset sources. in all the tables describing the different registers, the reset source is indicated. internal reset signals nresetpconf asserted reset source nresetglobal when enresetpconf is set to 0 when enrestpconf is set to 1 nresetsleep nresetcold por asserted asserted asserted asserted asserted nreset pin asserted asserted asserted asserted asserted porta input asserted - asserted - - watchdog asserted - asserted - - buserror asserted - asserted - - sleep - - - asserted - table 6-5. internal reset assertion as a function of the reset source. 6.5 reset source description 6.5.1 power on reset the power on reset (por) monitors the external supply voltage. it activates a reset on a rising edge of this supply voltage. the reset is inactivated only if the internal vo ltage regulator has started up. the por block performs no precise voltage level detection. 6.5.2 nreset pin applying a low input state on the nreset pin can activate the reset. 6.5.3 programmable port a input combination port a (if present in the product) can generate a reset signal. see the description of the port a for further information. 6.5.4 watchdog reset the watchdog will genera te a reset if the enresetwd bit in the regsysctrl register has been set and if the watchdog is not cleared in time by the processor. see chapter 6.8 describing the watchdog for further information.
? semtech 2006 www.semtech.com 6-5 xe8806a/xe8807a 6.5.5 buserror reset the address space is assigned as shown in the register map of the product. if the enbuserror bit in the regsysctrl register is set and the software accesses an unused address, a reset is generated. 6.6 sleep mode entering the sleep mode will reset a part of the circuit. the re set is used to configure the circuit for correct wake-up after the sleep mode. if the sleepen bit in the regsysctrl register has been set, the sleep mode can be entered by setting the bit sleep in regsysreset . during the sleep mode, the nresetsleep signal is active. for detailed information on the sleep mode, see the system documentation. 6.7 control register description and operation two registers are dedicated for reset status and control, regsysreset and regsysctrl . the bits sleep, sleepflag and sleepen are also located in those registers and are described in the chapter dedicated to the different operating modes of the circuit (system block). the regsysreset register gives information on the source that generated the last reset. it can be read at the beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if the circuit is starting up normally. ? when resetbuserror is 1, a forbidden address access generated the reset. ? when resetwd is 1, the watchdog generated the reset. ? when resetfromporta is 1, a porta combination generated the reset. note: if no bit is set to 1, the reset source was either the nreset pin or the internal por. note: several bits might be set or not, if the register was not cleared in between 2 reset occurrences. the two other bits concern the sleep mode control and information (see sy stem documentation for the sleep mode description). ? when sleepflag is 1, the sleep mode was active before the reset occurred. this bit will always appear together with the resetfromporta bit since all other possibilities to leave the sleep mode (por and nreset pin) will clear the sleepflag . ? when sleep is set to 1, and sleepen is 1, the sleep mode is entered. the bit always reads back a 0. the regsysctrl register enables the different available reset sources and the sleep mode. ? enbuserror enables the reset due to a bus error condition. ? enresetwd enables the reset due to the watchdog (can not be disabled once enabled). ? enresetpconf enables the reset of the port configurations when reset by port a, a bus error or the watchdog. ? sleepen unlocks the sleep bit. as long as sleepen is 0, the sleep bit has no effect. 6.8 watchdog the watchdog is a timer, which has to be cleared at least every 2 seconds by the software to prevent a reset to be generated by the timeout condition. the watchdog can be enabled by software by setting the enresetwd bit in the regsysctrl register to 1. it can then only be disabled by a power on reset or by setting the nreset pin to a low state. the watchdog timer can be cleared by writin g consecutively the values hx0a and hx03 to the regsyswd register. the sequence must strictly be resp ected to clear the watchdog.
? semtech 2006 www.semtech.com 6-6 xe8806a/xe8807a in assembler code, the sequence to clear the watchdog is: move addrregsyswd, #0x0a move addrregsyswd, #0x03 only writing hx0a followed by hx03 resets the wd . if some other write instruction is done to the regsyswd between the writing of the hx0a and hx03 valu es, the watchdog timer will not be cleared. it is possible to read the status of the watchdog in the regsysw d register. the watchdog is a 4 bit counter with a count range between 0 and 7. the system reset is generated when the counter is reaching the value 8. 6.9 start-up and watchdog specifications at start-up of the circuit, the por block generates a reset signal during t por . the circuit starts software execution after this period (see system chapter). the por is intended to force the circuit into a co rrect state at start-up. for precise monitoring of the supply voltage, the voltage level detector (vld) has to be used. symbol parameter min typ max unit comments t por por reset duration 5 20 ms vbat_sl supply ramp up 0.5 v/ms 1 wdtime watchdog timeout period 2 s 2 table 6. electrical and timing specifications note: 1) the vbat_sl defines the minimum slope required on vbat. correct start-up of the circuit is not guaranteed if this slope is too slow. in such a case, a delay has to be built using the nreset pin. note: 2) the minimal watchdog timeout per iod is guaranteed when t he internal oscillators are used. in case an external clock source is used, t he watchdog timeout period will be correct in so fa r the contents of the regsysrctrim1 and regsysrctrim2 registers are correct (see clock block documentation for more details).
? semtech 2006 www.semtech.com 7-1 xe8806a/xe8807a 7. clock generation 7. clock generation ............................................................................................................ .................... 7-1 7.1 feat ures ................................................................................................................... .......................... 7-2 7.2 over view ................................................................................................................... ......................... 7-2 7.3 regist er map............................................................................................................... ....................... 7-2 7.4 interrupts an d events map .................................................................................................. ............... 7-3 7.5 clock sources.............................................................................................................. ....................... 7-5 7.6 rc osc illator.............................................................................................................. ......................... 7-5 7.6.1 config uration............................................................................................................ .......................... 7-5 7.6.2 rc oscillator frequency tuning ........................................................................................... ................ 7-5 7.6.3 rc oscillator specifications ............................................................................................. ................... 7-6 7.7 xtal o scillator............................................................................................................ .......................... 7-7 7.7.1 xtal c onfiguration ....................................................................................................... ........................ 7-7 7.7.2 xtal oscillato r specifications ........................................................................................... .................... 7-7 7.8 external clock............................................................................................................. ........................ 7-8 7.8.1 external cloc k configuration ............................................................................................. .................. 7-8 7.8.2 external clock specification............................................................................................. ................... 7-8 7.9 clock source selection ..................................................................................................... .................. 7-8 7.10 prescalers ................................................................................................................ .......................... 7-9 7.11 32 khz frequ ency selector ................................................................................................. .............. 7-10
? semtech 2006 www.semtech.com 7-2 xe8806a/xe8807a 7.1 features 3 available clock sources (rc oscillator, quartz oscillator and external clock). - 2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). - cpu clock disabling in halt mode. 7.2 overview the xe88lcxx chips can work on different clock sour ces (rc oscillator, qua rtz oscillator and external clock). the clock generator block is in charge of distributi ng the necessary clock frequencies to the circuit. figure 7-1 represents the functio nality of the clock block. the internal rc oscillator or an extern al clock source can be selected to dr ive the high prescaler. this prescaler generates frequency divisions down to 1/256 of its input frequency. a 32khz clock is generated by enabling the quartz oscillator (if present in the product) or by sele cting the appropriate tap on the high prescaler. the low prescaler generates clock signals from 32khz down to 1h z. the clock source for the cpu can be selected from the rc oscillator, the external clock or the 32khz clock. 7.3 register map pos. regsysclock rw reset function 7 cpusel r/w 0 nresetsleep select speed for cpuck 6 - r 0 unused 5 enextclock r/w 0 nresetcold enable for external clock 4 biasrc r/w 1 nresetcold enable rcbias (reduces start-up time of rc). 3 coldxtal r 1 nresetsleep xtal in start phase 2 - r 0 unused 1 enablextal r/w 0 nresetsleep enable xtal oscillator 0 enablerc r/w 1 nresetsleep enable rc oscillator table 7-1: regsysclock register pos. regsysmisc rw reset function 7-2 -- r 000000 unused 1 output16k r/w 0 nresetsleep output 16 khz signal on pb[3] 0 outputcpuck r/w 0 nresetsleep output cpu clock on pb[2] table 7-2: regsysmisc register pos. regsyspre0 rw reset function 7-1 -- r 0000000 unused 0 clearlowprescal w1 r0 0 write 1 to reset low prescaler, but always reads 0 table 7-3: regsyspre0 register
? semtech 2006 www.semtech.com 7-3 xe8806a/xe8807a pos. regsysrctrim1 rw reset function 7-5 -- r 000 unused 4 rcfreqrange r/w 0 nresetcold low/high freq. range (low=0) 3 rcfreqcoarse[3] r/w 0 nresetcold rc coarse trim bit 3 2 rcfreqcoarse[2] r/w 0 nresetcold rc coarse trim bit 2 1 rcfreqcoarse[1] r/w 0 nresetcold rc coarse trim bit 1 0 rcfreqcoarse[0] r/w 1 nresetcold rc coarse trim bit 0 table 7-4: regsysrctrim1 register pos. regsysrctrim2 rw reset function 7-6 -- r 00 unused 5 rcfreqfine[5] r/w 0 nresetcold rc fine trim bit 5 4 rcfreqfine[4] r/w 0 nresetcold rc fine trim bit 4 3 rcfreqfine[3] r/w 0 nresetcold rc fine trim bit 3 2 rcfreqfine[2] r/w 0 nresetcold rc fine trim bit 2 1 rcfreqfine[1] r/w 0 nresetcold rc fine trim bit 1 0 rcfreqfine[0] r/w 0 nresetcold rc fine trim bit 0 table 7-5: regsysrctrim2 register pos. regsysptckmode rw reset function 7-1 -- r 0000000 unused 0 reserved r/w 0 nresetglobal reserved table 7-6: regsysptckmode register 7.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager ck128hz regirqhig(6) regevn(5) ck1hz regirqmid(3) regevn(1) table 7-7: interrupts and events map
? semtech 2006 www.semtech.com 7-4 xe8806a/xe8807a rc ext div. by 2 high prescaler lo w prescaler xtal system clock ck32khz en ab le rc o r en ext clo ck enablextal and not(enextclock) en ext clo ck cpu sel cpuck ck32khz ... ck1hz ckrcext ... ckrcext/256 0 1 0 1 1 0 0 1 regsysrctrim1&2 ckrcext figure 7-1. clock block structure
? semtech 2006 www.semtech.com 7-5 xe8806a/xe8807a 7.5 clock sources 7.6 rc oscillator 7.6.1 configuration the rc oscillator is always turned on and selected for cpu and system operation at power-on reset, pad nreset, and when exiting sl eep mode. it can be turned off after the xtal (quartz oscillat or) has been started, after selection of the external cloc k or by entering sleep mode. the rc oscillator has two frequency ranges: sub-mhz ( 50 khz to 0.5 mhz) and above-mhz (0.5 mhz to 5 mhz). inside a range, the frequency can be tuned by softw are for coarse and fine adjustment. see registers regsysrctrim1 and regsysrctrim2 . bit enablerc in register regsysclock controls the propagation of the rc clock signal and the operation of the oscillator. the user can stop the rc oscillator by resetting the bit enablerc . entering the sleep mode disables the rc oscillator. note : the rc oscillator bias can be maintained while the oscillator is disabled by setting the bit biasrc in regsysclock . this allows a faster restart of the rc oscillator at the cost of increased power consumption (see section 7.6.3). 7.6.2 rc oscillator frequency tuning the rc oscillator frequency can be set using the bits in the regsysrctrim1 and regsysrctrim2 registers. figure 7-2 shows the nominal fr equency of the rc oscillator as a function of these bits . the absolute value of the frequency for a given register content may change by 35% from chip to chip due to the tolerances on the integrated capacitors and resistors. however, the modifica tion of the frequency as a function of a modification of the register content is fairly precise. this means that the curves in figur e 7-2 can shift up and down but that the slope remains unchanged. the bit rcfreqrange modifies the oscillator frequency by a fa ctor of 10. the upper curve in the figure corresponds to rcfreqrange =1. the rcfreqcoarse modifies the frequency of the oscillator by a factor ( rcfreqcoarse +1). the figure represents the frequency for 5 different values of the bits rcfreqcoarse : for each value the frequency is multiplied by 2. incrementing the rcfreqfine code, increases the frequency by about 1.4%. the frequency of the oscillator is therefor given by: f rc =f rcmin ? (1+9 ? rcfreqrange ) ? (1+ rcfreqcoarse ) ? (1.014) rcfreqfine with f rcmin the rc oscillator frequency if the registers are all 0.
? semtech 2006 www.semtech.com 7-6 xe8806a/xe8807a 0 0 0000 01 0 0 0 0 1 0 0000 1 1 0000 11 1 11 1 0 1 0 00 0 1 00000 1 1 0000 1 1 1 1 11 010000 1 00 0 0 0 1 10 0 0 0 111111 01 0 00 0 10 0 00 0 1 1 00 0 0 111111 01 0 000 1 0 0 0 00 110000 1 1 1 11 1 0 0 0 0 00 0 1000 0 1 00 0 00 1 10 0 00 11 1 1 11 01 0 000 1 0000 0 11 0 0 0 0 111 1 11 01 0 000 1 0 00 0 0 1 1 00 0 0 1 11 1 1 1 01 0 00 0 10 0 0 00 1 1 0000 1 1 1 11 1 01 0 0 0 0 1 0 0 0 00 1 1 0000 1 1 1 1 11 0000 0001 0011 0111 1111 1e+04 1e+05 1e+06 1e+07 rcfreqcoarse(3:0) nominal rc oscillator frequency [hz] rcfreqrange='1' rcfreqrange='0' rcfreqfine(5:0) rcfreqfine(5:0) figure 7-2. rc oscillator nominal frequency tuning. 7.6.3 rc oscillato r specifications sym description min typ max unit comments f rcmin lowest rc frequency 25 40 55 khz note 1 rcfreqfine fine tuning step 1.4 2.0 % rc_su startup time 30 50 us biasrc =0 3 5 us biasrc =1 psrr @ dc supply voltage tbd %/v note 2 dependence tbd %/v note 3 ? f/ ? t temperature dependence 0.1 %/ c table 7-8. rc oscillator specifications note 1: this is the frequency tolerance when all trimming code s are 0. the frequency at start-up is about twice as high. note 2: frequency shift as a function of vbat with normal regulator function. note 3: frequency shift as a function of vbat while the regulator is short-circuited to vbat. the tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the software or hardware dfll (digital frequency locked l oop) which uses the crystal oscillator as a reference frequency.
? semtech 2006 www.semtech.com 7-7 xe8806a/xe8807a 7.7 xtal oscillator 7.7.1 xtal configuration the xtal operates with an external crystal of 32?768 hz. du ring xtal oscillator start-up, the first 32768 cycles are masked. the two bits enablextal and coldxtal in register regsysclock control the oscillator. at power-on reset, a pad nreset pulse or during sleep mode, enablextal is reset and coldxtal is set (xtal oscillator is not selected at start-up). the user can star t xtal oscillator by setting enablextal . when the xtal oscillator starts, bit coldxtal is reset after 32768 cycles. before coldxtal is reset by the system, the xtal frequency precision is not guaranteed. the xtal osc illator can be stopped by the user by resetting bit enablextal . when the user enters into slee p mode, the xtal is stopped. 7.7.2 xtal oscillator specifications the crystal oscillator has been designed for a crystal with the specifications given in table 7-9. the oscillator precision can only be guaranteed for this crystal. symbol description min typ max unit comments fs resonance frequency 32768 hz cl cl for nominal frequency 8.2 15 pf rm motional resistance 40 100 k ? cm motional capacitance 1.8 2.5 3.2 ff c0 shunt capacitance 0.7 1.1 2.0 pf rmp motional resistance of 6 th overtone (parasitic) 4 8 k ? q quality factor 30k 50k 400k - table 7-9. crystal specifications. for safe operation, low power consumption and to meet the specified precision, careful board layout is required: keep lines xin and xout short and insert a vss line in between them. connect the crystal package to vss. no noisy or digital lines near xin or xout. insert guards where needed. respect the board specifications of table 7-10. symbol description min typ max unit comments rh_xin resistance xin-vss 10 m ? rh_xout resistance xout- vss 10 m ? rh_xin_xout resistance xin- xout 50 m ? cp_xin capacitance xin- vss 0.5 3.0 pf cp_xout capacitance xout- vss 0.5 3.0 pf cp_xin_xout capacitance xin- xout 0.2 1.0 pf table 7-10. board layout specifications.
? semtech 2006 www.semtech.com 7-8 xe8806a/xe8807a the oscillator characteristics are given in table 7-11. the characteristics ar e valid only if the crystal and board layout meet the specifications above. symbol description min typ max unit comments f xtal nominal frequency 32768 hz st_xtal start-up time 1 2 s fstab frequency deviation -100 300 ppm note 1 table 7-11. crystal osc illator characteristics. note 1. this gives the relative frequency deviation from nominal for a crystal with cl=8.2pf and within the temperature range -40 c to 85 c. the crystal tolerance, crystal aging and crystal temperature drift are not included in this figure. 7.8 external clock 7.8.1 external clock configuration the user can provide an external clock instead of the in ternal oscillators. the external provided frequency is internally divided by two. the ex ternal clock input pin is xin. the system is configured for external clock by bit enextclock in register regsysclock . using the bits in the registers regsysrctrim1 and regsysrctrim2 , the ck32khz clock frequency can be controlled (see section 7.11). note: when using the external clock, the xtal is not available. 7.8.2 external clock specification the external clock has to satisfy the specifications in the table below. correct behavior of the circuit can not be guaranteed if the external clock signal do es not respect the specifications below. symbol description min typ max unit comments f ext external clock frequency 8 mhz note 1 pw_1 pulse 1 width 0.06 s note 1 pw_0 pulse 0 width 0.03 20 s note 1 f ext_lv external clock frequency tbd khz note 2 pw_1_lv pulse 1 width tbd s note 2 pw_0_lv pulse 0 width tbd 20 s note 2 table 7-12. external clock specifications. note 1 . for vbat 2.4v note 2 . for vbat=vreg=1.2v 7.9 clock source selection there are three possible cloc k sources available for the cpu clock. t he rc clock is always selected after power- up, a negative pulse on nreset or after sleep mode. the cpu clock selection is done with the bit cpusel in regsysclock (0= fastest clock, 1= 32 khz from xtal if enablextal =1 and enextclock = 0 else from high prescaler 32 khz output). switching from one clock source to another is glitch free.
? semtech 2006 www.semtech.com 7-9 xe8806a/xe8807a the next table summarizes the different clock configurations of the circuit: clock sources clock targets cpuck mode name enextclock enablerc enablextal cpusel =0 cpusel =1 high prescaler clock input low prescaler clock input sleep 0 0 0 off off off off xtal 0 0 1 xtal xtal off xtal rc 0 1 0 rc note 2 high presc. rc high presc. rc + xtal 0 1 1 rc note 1 and 2 xtal rc note 1 xtal external 1 x x external note 2 high presc. external high presc. table 7-13: table of clocking modes. note 1: the frequency of the rc must be higher than 100 khz when xtal is enabled in order to ensure a proper 32 khz operation. note 2: the clock rc can be divided by the value of freq in struction (see coolrisc in struction information) freq instruction cpuck nodiv rc or external div2 rc/2 or external/2 div4 rc/4 or external/4 div8 rc/8 or external/8 div16 rc/16 or external/16 note 3: switching from one clock source to another and st opping the unused clock source must be performed using 2 move instructions to regsysclock . first select the new clock sour ce and then stop the unused one. 7.10 prescalers the clock generator block embeds two divider chains: the high prescaler and the low one. the high prescaler is made of an 8 stage dividing chai n and the low prescaler of a 15 stage dividing chain. features: ? high prescaler can only be driven wi th rc clock or external clock (bits enablerc or enextclock have to be set, see table 7-13). ? low prescaler can be driven from the high presca ler or directly with the xtal clock when bit enablextal is set to 1 and bit enextclock is set to 0. ? bit clearlowprescal in the regsyspre0 register allows to reset synchr onously the low prescaler, the low prescaler is also automatically cleared when bit enablextal is set. both dividing chains are reset asynchronously by the nresetglobal signal. ? bit coldxtal =1 indicates the xtal is in its start phase. it is active for 32768 xtal cycles after setting enablextal .
? semtech 2006 www.semtech.com 7-10 xe8806a/xe8807a 7.11 32 khz frequency selector a decoder is used to select from the high prescaler, the frequency tap that is the closest to 32 khz to operate the low prescaler when the xtal is not running. in this case, the rc oscillator frequency of 35% will also be valid for the low prescaler frequency outputs. the next table shows how the rc trimming values in the regsysrctrim1 and regsysrctrim2 registers select the 32 khz frequency. the least significant bits of the rcfreqfine word are not used. in order to ensure the correct frequency selection for t he low prescaler when having an external clock, a proper value must be set in the rc trim registers. the code ca n be selected from the table below as a function of the frequency ratio between half the frequency of the external clock and 32khz. if the frequency is not set correctly, all timings derived from the low prescaler will be shi fted accordingly (e.g. watc hdog frequencies ) and some peripherals may no longer function correctly if the devia tion from 32khz is too large (e.g. the voltage level detector).
? semtech 2006 www.semtech.com 7-11 xe8806a/xe8807a rcfreqrange&rcfreqcoarse(3:0)&rcfreqfine(5:3) selected high prescaler tap default case (0?0001?000) ckrcext/2 from 0?0000?000 to 0?0000?100 ckrcext from 0?0000?101 to 0?0001?100 ckrcext/2 from 0?0001?101 to 0?0001?111 ckrcext/4 0?0010?000 ckrcext/2 from 0?0010?001 to 0?0010?110 ckrcext/4 0?0010?111 ckrcext/8 from 0?0011?000 to 0?0011?100 ckrcext/4 from 0?0011?101 to 0?0011?111 ckrcext/8 from 0?0100?000 to 0?1000?010 ckrcext/4 from 0?0100?011 to 0?0100?111 ckrcext/8 0?0101?000 ckrcext/4 from 0?0101?001 to 0?0101?110 ckrcext/8 0?0101?111 ckrcext/16 from 0?0110?000 to 0?0110?101 ckrcext/8 from 0?0110?110 to 0?0110?111 ckrcext/16 from 0?0111?000 to 0?0111?100 ckrcext/8 from 0?0111?101 to 0?0111?111 ckrcext/16 from 0?1000?000 to 0?1000?011 ckrcext/8 from 0?1000?100 to 0?1000?111 ckrcext/16 from 0?1001?000 to 0?1001?010 ckrcext/8 from 0?1001?011 to 0?1001?111 ckrcext/16 from 0?1010?000 to 0?1010?001 ckrcext/8 from 0?1010?010 to 0?1010?111 ckrcext/16 0?1011?000 ckrcext/8 from 0?1011?001 to 0?1011?110 ckrcext/16 0?1011?111 ckrcext/32 from 0?1100?000 to 0?1100?110 ckrcext/16 0?1100?111 ckrcext/32 from 0?1101?000 to 0?1101?101 ckrcext/16 from 0?1101?110 to 0?1101?111 ckrcext/32 from 0?1110?000 to 0?1110?100 ckrcext/16 from 0?1110?101 to 0?1110?111 ckrcext/32 from 0?1111?000 to 0?1111?100 ckrcext/16 from 0?1111?101 to 0?1111?111 ckrcext/32 from 1?0000?000 to 1?0000?010 ckrcext/8 from 1?0000?011 to 1?0001?010 ckrcext/16 from 1?0001?011 to 1?0010?100 ckrcext/32 from 1?0010?101 to 1?0010?111 ckrcext/64 from 1?0011?000 to 1?0011?010 ckrcext/32 from 1?0011?011 to 1?0011?111 ckrcext/64 1?0100?000 ckrcext/32 from 1?0100?001 to 1?0100?110 ckrcext/64 1?0100?111 ckrcext/128 from 1?0101?000 to 1?0101?100 ckrcext/64 from 1?0101?101 to 1?0101?111 ckrcext/128 from 10110?000 to 1?0110?011 ckrcext/64 from 1?0110?100 to 1?0110?111 ckrcext/128 from 1?0111?000 to 1?0111?010 ckrcext/64 from 1?0111?011 to 1?0111?111 ckrcext/128 from 1?1000?000 to 1?1000?001 ckrcext/64 from 1?1000?010 to 1?1000?111 ckrcext/128 1?1001?000 ckrcext/64 from 1?1001?001 to 1?1111?111 ckrcext/128 table 7-14: table of 32khz high prescaler tap decoder.
? semtech 2006 www.semtech.com 8-1 xe8806a/xe8807a 8. interrupt handler 8.1 f eatures ............................................................................................................................... ........... 8-2 8.2 o verview ............................................................................................................................... .......... 8-2 8.3 r egister map ............................................................................................................................... .... 8-2 8.4 d etailed description ...................................................................................................................... 8-4 8.5 i nterrupt handling software ........................................................................................................ 8-5
? semtech 2006 www.semtech.com 8-2 xe8806a/xe8807a 8.1 features the xe8000 chips support 24 inte rrupt sources, divided into 3 levels of priority. 8.2 overview the interrupt handler allows 24 interrupt sources to be managed individually. the 24 interrupt sources are divided into 3 levels of priori ty: high (8 interrupt sources), mid (8 interrupt sources), and low (8 interrupt sources). those 3 levels of priority are directly mapped to those supported by the coolrisc? (in0, in1 and in2; see coolrisc documentation for more information). additional functions are given that allow fast detection of the highest priority interrupt that has been activated. 8.3 register map register name regirqhig regirqmid regirqlow regirqenhig regirqenmid regirqenlow regirqpriority regirqirq table 8-1: irq handler registers pos. regirqhig rw reset function 7 regirqhig[7] r c1 0 nresetglobal interrupt #23 (high priority) clear interrupt #23 when 1 is written 6 regirqhig[6] r c1 0 nresetglobal interrupt #22 (high priority) clear interrupt #22 when 1 is written 5 regirqhig[5] r c1 0 nresetglobal interrupt #21 (high priority) clear interrupt #21 when 1 is written 4 regirqhig[4] r c1 0 nresetglobal interrupt #20 (high priority) clear interrupt #20 when 1 is written 3 regirqhig[3] r c1 0 nresetglobal interrupt #19 (high priority) clear interrupt #19 when 1 is written 2 regirqhig[2] r c1 0 nresetglobal interrupt #18 (high priority) clear interrupt #18 when 1 is written 1 regirqhig[1] r c1 0 nresetglobal interrupt #17 (high priority) clear interrupt #17 when 1 is written 0 regirqhig[0] r c1 0 nresetglobal interrupt #16 (high priority) clear interrupt #16 when 1 is written table 8-2: regirqhig
? semtech 2006 www.semtech.com 8-3 xe8806a/xe8807a pos. regirqmid rw reset function 7 regirqmid[7] r c1 0 nresetglobal interrupt #15 (mid priority) clear interrupt #15 when 1 is written 6 regirqmid[6] r c1 0 nresetglobal interrupt #14 (mid priority) clear interrupt #14 when 1 is written 5 regirqmid[5] r c1 0 nresetglobal interrupt #13 (mid priority) clear interrupt #13 when 1 is written 4 regirqmid[4] r c1 0 nresetglobal interrupt #12 (mid priority) clear interrupt #12 when 1 is written 3 regirqmid[3] r c1 0 nresetglobal interrupt #11 (mid priority) clear interrupt #11 when 1 is written 2 regirqmid[2] r c1 0 nresetglobal interrupt #10 (mid priority) clear interrupt #10 when 1 is written 1 regirqmid[1] r c1 0 nresetglobal interrupt #9 (mid priority) clear interrupt #9 when 1 is written 0 regirqmid[0] r c1 0 nresetglobal interrupt #8 (mid priority) clear interrupt #8 when 1 is written table 8-3: regirqmid pos. regirqlow rw reset function 7 regirqlow[7] r c1 0 nresetglobal interrupt #7 (low priority) clear interrupt #7 when 1 is written 6 regirqlow[6] r c1 0 nresetglobal interrupt #6 (low priority) clear interrupt #6 when 1 is written 5 regirqlow[5] r c1 0 nresetglobal interrupt #5 (low priority) clear interrupt #5 when 1 is written 4 regirqlow[4] r c1 0 nresetglobal interrupt #4 (low priority) clear interrupt #4 when 1 is written 3 regirqlow[3] r c1 0 nresetglobal interrupt #3 (low priority) clear interrupt #3 when 1 is written 2 regirqlow[2] r c1 0 nresetglobal interrupt #2 (low priority) clear interrupt #2 when 1 is written 1 regirqlow[1] r c1 0 nresetglobal interrupt #1 (low priority) clear interrupt #1 when 1 is written 0 regirqlow[0] r c1 0 nresetglobal interrupt #0 (low priority) clear interrupt #0 when 1 is written table 8-4: regirqlow pos. regirqenhig rw reset function 7 regirqenhig[7] rw 0 1= enable interrupt #23 6 regirqenhig[6] rw 0 1= enable interrupt #22 5 regirqenhig[5] rw 0 1= enable interrupt #21 4 regirqenhig[4] rw 0 1= enable interrupt #20 3 regirqenhig[3] rw 0 1= enable interrupt #19 2 regirqenhig[2] rw 0 1= enable interrupt #18 1 regirqenhig[1] rw 0 1= enable interrupt #17 0 regirqenhig[0] rw 0 1= enable interrupt #16 table 8-5: regirqenhig
? semtech 2006 www.semtech.com 8-4 xe8806a/xe8807a pos. regirqenmid rw reset function 7 regirqenmid[7] rw 0 1= enable interrupt #15 6 regirqenmid[6] rw 0 1= enable interrupt #14 5 regirqenmid[5] rw 0 1= enable interrupt #13 4 regirqenmid[4] rw 0 1= enable interrupt #12 3 regirqenmid[3] rw 0 1= enable interrupt #11 2 regirqenmid[2] rw 0 1= enable interrupt #10 1 regirqenmid[1] rw 0 1= enable interrupt #9 0 regirqenmid[0] rw 0 1= enable interrupt #8 table 8-6: regirqenmid pos. regirqenlow rw reset function 7 regirqenlow[7] rw 0 1= enable interrupt #7 6 regirqenlow[6] rw 0 1= enable interrupt #6 5 regirqenlow[5] rw 0 1= enable interrupt #5 4 regirqenlow[4] rw 0 1= enable interrupt #4 3 regirqenlow[3] rw 0 1= enable interrupt #3 2 regirqenlow[2] rw 0 1= enable interrupt #2 1 regirqenlow[1] rw 0 1= enable interrupt #1 0 regirqenlow[0] rw 0 1= enable interrupt #0 table 8-7: regirqenlow pos. regirqpriority rw reset function 7-0 regirqpriority r 11111111 code of highest priority set table 8-8: regirqpriority pos. regirqirq rw reset function 7-3 - r 00000 unused 2 irqhig r 0 one or more high priority interrupts is set 1 irqmid r 0 one or more mid priority interrupts is set 0 irqlow r 0 one or more low priority interrupts is set table 8-9: regirqirq 8.4 detailed description the coolrisc core has 3 different interrupt levels in 0, in1 and in2 (figure 8-1). when these interrupts are triggered, the program counter (pc) is loaded with a fi xed address. in case more than one interrupt occurs simultaneously, the execution order is in0, in1, in2. the masking, setting and clearing of these interrupts can be done in the stat register (see chapter describing the cpu). the interrupt handler bundles a certain number of interru pt sources and routes them to one of these three interrupts and provides the possibility to enable/ disable each of them individually . the definition of the interrupt sources is given in the memory mapping chapter. regirqhig, regirqmid, and r egirqlow are 8-bit registers c ontaining flags for the interrupt sources. those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers regirqenhig , regirqenmid or regirqenlow is set) and a rising edge is detected on the corresponding interrupt source.
? semtech 2006 www.semtech.com 8-5 xe8806a/xe8807a once memorized, an interrupt flag can be cleare d by writing a ?1? in the corresponding bit of regirqhig , regirqmid or regirqlow . writing a ?0? does not modify the flag. to definitively clear the interrupt, one has to clear the coolrisc interrupt in the coolrisc stat register. all interrupts are automatically cleared after a reset. two registers are provided to facilitate the writing of interrupt service software. regirqpriority contains the number of the highest priority set (its value is 0xff when no interrupt is memorized). regirqirq indicates the priority level of the currently activated interrupts. all interrupt sources are sampled by the highest frequency in the system . a cpu interruption is generated and memorized when an interrupt becomes high. between the risi ng edge of the interrupt on the peripheral and the rising edge on the coolrisc core, there is a latency of one clock cycle. ie2 ie1 gie in2 in1 in0 ev1 ev0 stat low priority pc=h0002 medium priority pc=h0001 high priority pc=h0003 7 6 5 4 3 2 1 0 regirqhig ? ? regirqlow regirqmid 7 6 5 4 3 2 1 0 regirqenhig interrupt sources figure 8-1. principle of the interrupt handler. 8.5 interrupt handling software this chapter describes an example of the software used for the interrupt handler. th is software is present by default in the software development environments. it represent s only one of several possible ways of handling the interrupts.
? semtech 2006 www.semtech.com 8-6 xe8806a/xe8807a first of all, the jump addresses are def ined at the beginning of the crt0.s file. in our case, all three interrupt levels jump to the same place (defined by the _interr upt label), but this can be changed if required. ######################################################################## ## reset & interrupt vectors ######################################################################## _start: jump main_init ; reset jump _interrupt ; in1 jump _interrupt ; in2 jump _interrupt ; in0 the first thing to do when an interrupt is activated is to save the context. you have to start with saving the contents of the accumulator, then the flags and finally the internal cpu re gisters. you will find this part of the code in the irqcomon_xx.s file. _interrupt: ######################################################################## ## save all registers and flags ######################################################################## move -(i3), a move a, r0 sflag move -(i3), a move -(i3), ipl move -(i3), iph move -(i3), i0l move -(i3), i0h move -(i3), i1l move -(i3), i1h move -(i3), i2l move -(i3), i2h move -(i3), r0 move -(i3), r1 move -(i3), r2 move -(i3), r3 next step is to determine which interrupt is ac tivated. in this case, we use the value in the regirqpriority register to determine the highest priority interrupt that was activa ted. other ways can be used, especially when the priority order fixed in the hardware needs to be changed. you will find this part of the code in the irqcomon_xx.s file. in this example, the labels are used as defined for the xe8802. ######################################################################## ## the following lines enables the adress calculation of the interrupt ## table. where regirqpriority is the addres offset for the table. ## the regirqpriority valid values are between 0x00 until 0x017. the ## 0xff value should never exist. ######################################################################## move r0,regirqpriority calls _interrupttab ; save pc+1 in ip _interrupttab: add ipl,#0x05 ; add the offset, nb instr. before table addc iph,#0x00 ; propagate carry add ipl,r0 ; add the offset of the regirqpriority addc iph,#0x00 ; propagate carry rets ; put ip in pc ; interrupt table jump ret_int ; regirqpriority = 0x00 jump ret_int ; regirqpriority = 0x01 jump irq_pa2 ; regirqpriority = 0x02 jump irq_pa3 ; regirqpriority = 0x03 jump irq_cntd ; regirqpriority = 0x04 jump irq_cntb ; regirqpriority = 0x05
? semtech 2006 www.semtech.com 8-7 xe8806a/xe8807a jump irq_pa6 ; regirqpriority = 0x06 jump irq_pa7 ; regirqpriority = 0x07 jump irq_pa0 ; regirqpriority = 0x08 jump irq_pa1 ; regirqpriority = 0x09 jump irq_vld ; regirqpriority = 0x0a jump irq_1hz ; regirqpriority = 0x0b jump irq_pa4 ; regirqpriority = 0x0c jump irq_pa5 ; regirqpriority = 0x0d jump irq_usrtcond1 ; regirqpriority = 0x0e jump irq_usrtcond2 ; regirqpriority = 0x0f jump irq_uartrx ; regirqpriority = 0x10 jump irq_uarttx ; regirqpriority = 0x11 jump irq_cmpd ; regirqpriority = 0x12 jump irq_cntc ; regirqpriority = 0x13 jump irq_cnta ; regirqpriority = 0x14 jump irq_spi ; regirqpriority = 0x15 jump irq_128hz ; regirqpriority = 0x16 jump irq_ac ; regirqpriority = 0x17 the next steps are to clear the interrupt flag in the interr upt handler, to call the specific function for the identified interrupt source and to clear the interrupt in the stat r egister. this code can be found in the file irqsave0_xx.s. ######################################################################## irq_ac: move regirqhig, #0x80 calls handle_irq_ac jump ret_int0 ######################################################################## irq_128hz: move regirqhig, #0x40 calls handle_irq_128hz jump ret_int0 ######################################################################## irq_spi: move regirqhig, #0x20 calls handle_irq_spi jump ret_int0 ? ret_int0: clrb stat, #2 jump ret_int finally, the context and the pc have to be restored. this code can be f ound in the irqcomon_xx.s file. ret_int: ######################################################################## ## restore all registers and flags ######################################################################## move r3, (i3)+ move r2, (i3)+ move r1, (i3)+ move r0, (i3)+ move i2h, (i3)+ move i2l, (i3)+ move i1h, (i3)+ move i1l, (i3)+ move i0h, (i3)+ move i0l, (i3)+ move iph, (i3)+ move ipl, (i3)+ rflag (i3)+ move a, (i3)+ reti ######################################################################## ## end of interrupt handlers ########################################################################
? semtech 2006 www.semtech.com 9-1 xe8806a/xe8807a 9. event handler 9.1 features ....................................................................................................................... ............... 9-2 9.2 overview ....................................................................................................................... ............... 9-2 9.3 register map ............................................................................................................................ .. 9-2 9.4 detailed descriptio n .............................................................................................................. 9-3
? semtech 2006 www.semtech.com 9-2 xe8806a/xe8807a 9.1 features the xe8000 chips support 8 event sources, divided into 2 levels of priority. 9.2 overview an event is different from an interrupt in that it does not modify the progra m counter (pc). events are used by two microcontroller instructions. first of all, events are useful to wake-up the microcontrolle r when it is in halt. the software execution then simply resumes at the instruction next to the halt instruction. the second instructio n is the conditional jump on event (jev). the jump is executed if one of the event flags in the st at register is set. in all ot her cases, the occurrence of an event has no effect. the event handler allows 8 event sources to be managed indi vidually. the 8 event sources are divided into 2 levels of priority: high (4 event sources) a nd low (4 event sources). those 2 leve ls of priority are directly mapped to those supported by the coolrisc? (ev0and in1; s ee coolrisc documentation for more information). additional functions are given that allow fast detection of the highest priority even t that has been activated. 9.3 register map the addresses given in table 9-1 are the default values and may be different in some products. register name regevn regevnen regevnpriority regevnevn table 9-1: evn handler registers. pos. regevn rw reset function 7 regevn[7] r c1 0 nresetglobal event #7 (high priority) clear event #7 when written 1 6 regevn[6] r c1 0 nresetglobal event #6 (high priority) clear event #6 when written 1 5 regevn[5] r c1 0 nresetglobal event #5 (high priority) clear event #5 when written 1 4 regevn[4] r c1 0 nresetglobal event #4 (high priority) clear event #4 when written 1 3 regevn[3] r c1 0 nresetglobal event #3 (low priority) clear event #3 when written 1 2 regevn[2] r c1 0 nresetglobal event #2 (low priority) clear event #2 when written 1 1 regevn[1] r c1 0 nresetglobal event #1 (low priority) clear event #1 when written 1 0 regevn[0] r c1 0 nresetglobal event #0 (low priority) clear event #0 when written 1 table 9-2: regevn
? semtech 2006 www.semtech.com 9-3 xe8806a/xe8807a pos. regevnen rw reset function 7 regevnen[7] rw 0 nresetglobal 1= enable event #7 6 regevnen[6] rw 0 nresetglobal 1= enable event #6 5 regevnen[5] rw 0 nresetglobal 1= enable event #5 4 regevnen[4] rw 0 nresetglobal 1= enable event #4 3 regevnen[3] rw 0 nresetglobal 1= enable event #3 2 regevnen[2] rw 0 nresetglobal 1= enable event #2 1 regevnen[1] rw 0 nresetglobal 1= enable event #1 0 regevnen[0] rw 0 nresetglobal 1= enable event #0 table 9-3: regevnen pos. regevnpriority rw reset function 7-0 regevnpriority r 11111111 nresetglobal code of highest event set ff if no event present. table 9-4: regevnpriority pos. regevnevn rw reset function 7-2 - r 00000 unused 1 evnhig r 0 nresetglobal one or more high priority event is set 0 evnlow r 0 nresetglobal one or more low priority event is set table 9-5: regevnevn 9.4 detailed description the coolrisc core has 2 different event levels ev0 and ev1 (figure 9-1). the setting and clearing of these events can be done in t he stat register (see chapter describing the cpu). the event handler bundles a certain nu mber of event sources and routes them to one of these two events and provides the possibility to enable/disable each of them individually. the definiti on of the event sources is given in the memory mapping chapter. regevn is an 8-bit register containing flags for the event sources. those flags are set when the event is enabled (i.e. if the corresponding bit in the registers regevnen is set) and a rising edge is detected on the corresponding event source. once memorized, writing a ?1? in the corresponding bit of regevn clears an event flag. writing a ?0? does not modify the flag. all interrupts are auto matically cleared after a reset. two registers are pr ovided to facilitate the writin g of event service software. regevnpriority contains the number of the highest event set (its value is 0xff when no event is memorized). regevnevn indicates the priority level of the current events. all event sources are sampled by the highest frequency in the system. a cpu event is generated and memorized when an event becomes high. the 8 event sources are divided into 2 levels of priority: high (4 event sources) and low (4 event sources). those 2 levels of priority are di rectly mapped to those supported by the coolrisc (ev0 and ev1; see coolrisc documentation for more information).
? semtech 2006 www.semtech.com 9-4 xe8806a/xe8807a ie2 ie1 gie in2 in1 in0 ev1 ev0 stat 7 6 5 4 3 2 1 0 regevn 7 6 5 4 3 2 1 0 regevnen event sources figure 9-1. event handler principle.
? semtech 2006 www.semtech.com 10-1 xe8806a/xe8807a 10. low power ram 10.1 features .................................................................................................................. .............. 10-2 10.1.1 ov erview ................................................................................................................ ............... 10-2 10.2 register map.............................................................................................................. ........... 10-2
? semtech 2006 www.semtech.com 10-2 xe8806a/xe8807a 10.1 features 10.1.1 overview in order to save power consumption, 8 8-bit registers are provided in page 0. these memory locations should be reserved for often-updated variables. as they are real registers and not ram, power consumption is greatly reduced. 10.2 register map pos. reg00 rw reset function 7-0 reg00 rw 0 low-power data memory 7-0 reg01 rw 0 low-power data memory 7-0 reg02 rw 0 low-power data memory 7-0 reg03 rw 0 low-power data memory 7-0 reg04 rw 0 low-power data memory 7-0 reg05 rw 0 low-power data memory 7-0 reg06 rw 0 low-power data memory 7-0 reg07 rw 0 low-power data memory table 10-1: low power ram
? semtech 2006 www.semtech.com 11-1 xe8806a/xe8807a 11. port a 11.1 features ....................................................................................................................... ................. 11-2 11.2 o verview ............................................................................................................................... ..... 11-2 11.3 r egister map .............................................................................................................................. 1 1-3 11.4 i nterrupts and events map ....................................................................................................... 11-4 11.5 p ort a (pa) o peration .............................................................................................................. 11-4 11.6 p ort a electrical specification ............................................................................................... 11-6
? semtech 2006 www.semtech.com 11-2 xe8806a/xe8807a 11.1 features ? input port, 8 bits wide ? each bit can be set individually for debounced or direct input ? each bit can be set individually for pull-up or not ? snap-to-rail option for each input ? each bit is an interrupt request source on the rising or falling edge ? a system reset can be generated on an input pattern ? pa[0] and pa[1] can generate two event s for the cpu, individually maskable ? pa[0] to pa[3] can be used as clock inputs for the counters/timers/pwm (product dependent) 11.2 overview porta is a general purpose 8 bit wide digital input port, with interrupt capability. figure 11-1 shows its structure. figure 11-1: structure of port a vbat 1 0 resetfromporta 8x regpapullup regpadebounce regpain regpactrl regpaedge regpares1 regpares0 0 1 8x 1 00 01 11 10 0 interrupts events cntclocks 8 8 8 8 8 debounce 1 0 debfast (regpactrl(0)) 1khz 32khz 8 8 8 port a 8x regpasnaptorail vss logic 8
? semtech 2006 www.semtech.com 11-3 xe8806a/xe8807a 11.3 register map there are eight registers in port a (pa), namely regpain , regpadebounce , regpapullup , regpaedge , regpares0 , regpares1 , regpactrl and regpasnaptorail . table 11-2 to table 11-9 show the mapping of control bits and functionality of these registers. register name regpain regpadebounce regpaedge regpapullup regpares0 regpares1 regpactrl regpasnaptorail table 11-1: pa registers pos. regpain rw reset description 7:0 pain[7:0] r x pad pa[7] to pa[0] input value table 11-2: regpain pos. regpadebounce rw reset description 7:0 padebounce[7:0] r w 0 nresetpconf pa[7] to pa[0] 1: debounce enabled 0: debounce disabled table 11-3: regpadebounce pos. regpaedge rw reset description 7:0 paedge[7:0] r w 0 nresetglobal pa[7] to pa[0] edge configuration 0: positive edge 1: negative edge table 11-4: regpaedge pos. regpapullup rw reset description 7:0 papullup[7:0] r w 1 nresetpconf pa[7] to pa[0] pullup enable 0: pullup disabled 1: pullup enabled table 11-5: regpapullup pos. regpares0 rw reset description 7:0 pares0[7:0] r w 0 nr esetglobal pa[7] to pa[ 0] reset configuration table 11-6: regpares0 pos. regpares1 rw reset description 7:0 pares1[7:0] r w 0 nr esetglobal pa[7] to pa[ 0] reset configuration table 11-7: regpares
? semtech 2006 www.semtech.com 11-4 xe8806a/xe8807a pos. regpactrl rw reset description 7:1 [7:1] r 0000000 unused 0 debfast r w 0 nresetpconf 0 = slow debounce, 1 = fastdebounce table 11-8: regpactrl pos. regpasnaptorail rw reset description 7:0 pasnaptorail[7:0] rw 0 nreset pconf set snap-to-rail input on table 11-9: regpasnaptorail note : depending on the status of the enresetpconf bit in regsysctrl , regpaedge, regpadebounce and regpactrl can be reset by any of the possible system rese ts or only with power-o n reset and nreset pad. 11.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager pa_irqbus[5] regirqmid[5] pa_irqbus[4] regirqmid[4] pa_irqbus[1] regirqmid[1] regevn[4] pa_irqbus[0] regirqmid[0] regevn[0] pa_irqbus[7] regirqlow[7] pa_irqbus[6] regirqlow[6] pa_irqbus[3] regirqlow[3] pa_irqbus[2] regirqlow[2] 11.5 port a (pa) operation the port a input status (debounced or not) can be read from regpain . debounce mode: each bit in port a can be individually debounced by setting the corresponding bit in regpadebounce . after reset, the debounce function is disabled. after enabling the debounce r, the change of the input value is accepted only if height consecutive samples are identical. selection of the clock is done by bit debfast in register regpactrl . debfast clock filter 0 1khz 1 32khz table 11-10 : debounce frequency selection note: the tolerance on the debounce frequency depends on the selected clock source. when the external clock is used, the pulse width will be correct if t he input of the low prescaler is set to a frequency close to 32khz (see clock block documentation). pullups/snap-to-rail: different functions are possible depending on the value of the registers regpapullup and regpasnaptorail . when the corresponding bit in regpapullup is set to 0, the inputs are floating (pullup and pulldown resistors are disconnected). when the corresponding bit in regpapullup is 1 and in regpasnaptorail is 0, a pullup resistor is connected to the input pin. fina lly, when the corresponding bit in regpapullup is 1 and in regpasnaptorail is 1, the snap-to-rail function is active.
? semtech 2006 www.semtech.com 11-5 xe8806a/xe8807a the snap-to-rail function connects a pullup or pulldown resi stor to the input pin depending on the value forced on the input pin. this function can be used for instance when the input port is connected to a tristate bus. when the bus is floating, the pullup or pulldown maintains the bus in the last low impedance state before it became floating until another low impedance output drives the bus. it also reduces the power consumption with respect to a classic pullup since it selects the pullup or pulldown resistor so that it confirms the detected input state. the state of input pin is summarized in the table below. papullup[x] pasnaptorail[x] (last) externally forced pa[x] value pa[x] pull 0 x x floating 1 0 x pullup 1 1 0 pulldown 1 1 1 pullup table 11-11 : snap-to-rail port a starts up with the pullup resistor co nnected and the snap-to-rail function disabled. port a as an interrupt source: each port a input is an interrupt request source and can be set on rising or falling edge with the corresponding bit in regpaedge . after reset, the rising edge is selected for interr upt generation by default. the interrupt source can be debounced by setting register regpadebounce . the interrupt signals are sampled on the fastest clock in the circuit. in order to guarantee that the circuit detects the in terrupt, the minimal pulse length should be 1 cycle of this clock. note: care must be taken when modifying regpaedge because this register performs an edge selection. the change of this register may result in a transition, which may be interpreted as a valid interruption. port a as an event source: the interrupt signals of the pins pa[0] and pa[1] ar e also available as event s on the event controller. port a as a clock source (product dependent): images of the pa[0] to pa[3] input ports (debounc ed or not) are available as clock sources for the counter/timer/pwm peripheral. port a as a reset source: port a can be used to generate a system reset by placing a predetermined word on port a externally. the reset is built using a logical and of the 8 pares[x] signals: resetfromporta = pareset[7] and pareset[6 ] and pareset[5] and ... and pareset[0] pareset[x] is itself a logical function of the corresponding pin pa[x]. one of f our logical functions can be selected for each pin by writing into two registers regpares0 and regpares1 as shown in table 11-12. pares1[x] pares0[x] pareset[x] 0 0 0 0 1 pa[x] 1 0 not(pa[x]) 1 1 1 table 11-12: selection bits for reset signal a reset from port a can be inhibited by placing a 0 on both pares1[x] and pares0[x] for at least 1 pin. setting both pares1[x] and pares0[x] to 1, makes the reset independent of the value on the corresponding pin. setting both registers to hff, will reset the circuit independent from the port a input value. this makes it possible to do a reset by software.
? semtech 2006 www.semtech.com 11-6 xe8806a/xe8807a note: depending of the value of pa[0] to pa[7], changes to regpares0 and regpares1 can cause a reset. therefore it is safe to have always one (regpares0[x], regpares1[x]) equal to ?00? during the setting operations. 11.6 port a electri cal specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v r pu pull-up resistance 20 50 80 k ? cin input capacitance 2.5 pf note 1 note 1: this value is indicative only since it depends on the package. table 11-13. electrical specification
? semtech 2006 www.semtech.com 12-1 xe8806a/xe8807a 12. port b 12.1 features.................................................................................................................. .................... 12-2 12.2 overview .................................................................................................................. ................... 12-2 12.3 register map.............................................................................................................. ................. 12-2 12.4 port b capabilit ies ....................................................................................................... ................ 12-3 12.5 port b analog capability .................................................................................................. ............ 12-4 12.5.1 port b analog configuration ............................................................................................. ........... 12-4 12.5.2 port b analog f unction specif ication.................................................................................... ........ 12-5 12.6 port b functi on capability ................................................................................................ ............ 12-5 12.7 port b digita l capabilities............................................................................................... .............. 12-6 12.7.1 port b digita l configuration............................................................................................ .............. 12-6 12.7.2 port b digital f unction specification ................................................................................... .......... 12-7 12.8 low power comparators ..................................................................................................... ........ 12-7
? semtech 2006 www.semtech.com 12-2 xe8806a/xe8807a 12.1 features ? input / output / analog port, 8 bits wide ? each bit can be set individually for input or output ? each bit can be set individually for open-drain or push-pull ? each bit can be set individually for pull-up or not (for input or open-drain mode) ? in open-drain mode, pull-up is not active when corresponding pad is set to zero ? the 8 pads can be connected individually to four internal analog lines (4 line analog bus) ? two internal freq. (16 khz and cp uck) can be output on pb[2] and pb[3] product dependant: ? two pwm signal can be output on pads pb[0] and pb[1] ? the synchronous serial interface (usrt) uses pads pb[5], pb[4] ? the uart interface uses pads pb[6] and pb[7] for tx and rx 12.2 overview port b is a multi-purpose 8 bit input/output port. in additi on to digital behavior, all pins can be used for analog signals. each port terminal can be individually selected as di gital input or output or as analog for sharing one of four possible analog lines. 12.3 register map table 12-1 shows the port b registers. register name regpbout regpbin regpbdir regpbopen regpbpullup regpbana table 12-1: default port b registers
? semtech 2006 www.semtech.com 12-3 xe8806a/xe8807a pos. regpbout rw reset description in digital mode description in analog mode 7 ? 0 pbout[7-0] r w 0 nresetpconf pad pb[7-0] output value analog bus selection for pad pb[7-0] table 12-2: regpbout pos. regpbin rw reset description in digital mode description in analog mode 7 ? 0 pbin[7-0] r w x pad pb[7-0] input status unused table 12-3: regpbin pos. regpbdir rw reset description in digital mode description in analog mode 7 ? 0 pbdir [7-0] r w 0 nresetpconf pad pb[7-0] di rection (0=input) analog bus selection for pad pb[7-0] table 12-4 : regpbdir pos. regpbopen rw reset description in digital mode description in analog mode 7 ? 0 pbopen[7-0] r w 0 nresetpconf pad pb[7-0] open drain (1 = open drain) unused table 12-5: regpbopen pos. regpbpullup rw reset description in digital mode description in analog mode 7 ?0 pbpullup[7] r w 1 nresetpconf pull-up for pad pb[7-0 ] (1=active) connect pad pb[7-0] on selected ana bus table 12-6: regpbpullup pos. regpbana rw reset description in digital mode description in analog mode 7 ? 0 pbana [7-0] r w 0 nresetpconf set pb[7-0] in analog mode set pb[7-0] in analog mode table 12-7: regpbana note: depending on the status of the enrespconf bit in regsysctrl , the reset conditions of the registers are different. see the reset block documentation for more details on the nresetpconf signal. 12.4 port b capabilities port b utilization (priority) name high (analog) medium (functions) low (digital) (default) pb[7] analog uart rx i/o (with pull-up) pb[6] analog uart tx i/o (with pull-up) pb[5] analog usrt s1 i/o (with pull-up) pb[4] analog usrt s0 i/o (with pull-up) pb[3] analog 16 khz i/o (with pull-up) pb[2] analog clock cpu i/o (with pull-up) pb[1] analog pwm1 counter c (c+d) i/o (with pull-up) pb[0] analog pwm0 counter a (a+b) i/o (with pull-up) table 12-8: different port b functions
? semtech 2006 www.semtech.com 12-4 xe8806a/xe8807a table 12-8 shows the different usages that can be made of port b with the order of priority. if a pin is selected to be analog, it overwrites the function and digital set-up. if the pi n is not selected as analog, but a function is enabled, it overwrites the digital set-up. if neither the analog nor function is selected for a pin, it is used as an ordinary digital i/o. this is the default configuration at start-up. note: the presence of the functions is product dependent. 12.5 port b analog capability 12.5.1 port b analog configuration port b terminals can be attached to a 4 line analog bus by setting the pbana[x] bits to 1 in the regpbana register. the other registers then define the connect ion of these 4 analog lines to the different pads of port b. these can be used to implement a simple lcd driver or a/d converter. analog switching is available only when the circuit is powered with sufficient voltage (see specification below). below the specified supply voltage, only voltages that are close to vss or vbat can be switched. when pbana[x] is set to 1, one pad of the port b terminals is changed from digital i/o mode to analog. the usage of the registers regpbpullup , regpbout and regpbdir define the analog configuration (see table 12-9). when pbana[x] = 1 , then pbpullup[x] connects the pin to the analog bus. pbdir[x] and pbpout[x] select which of the 4 analog lines is used. analog bus selection pbdir[x] pbout[x] pbpullup[x] pb[x] selection on 0 0 1 analog line 0 0 1 1 analog line 1 1 0 1 analog line 2 1 1 1 analog line 3 x x 0 high impedance table 12-9: selection of the analog lines with regpbdir , regpbout and regpbpullup when pbana[x] = 1 example: set the pads pb[2] and pb[5] on the analog line 3. (the values x depend on the configuration of others pads) - apply high impedance in the analog mode (move regpbpullup,#0bxx0xx0xx) - go to analog mode (move regpbana,#0bxx1xx1xx) - select the analog line3 (move regpbdir,#0bxx1xx1xx and move regpbout,#0bxx1xx1xx) - apply the analog line to the output (move regpbpullup,#0bxx1xx1xx)
? semtech 2006 www.semtech.com 12-5 xe8806a/xe8807a 12.5.2 port b analog function specification the table below defines the on-resistance of the sw itches between the pin and the analog bus for different conditions. the series resistance between 2 pins of port b connected to the same analog line is twice the resistance given in the table. sym description min typ max unit comments ron switch resistance 11 k ? note 1 ron switch resistance 15 k ? note 2 cin input capacitance (off) 3.5 pf note 3 cin input capacitance (on) 4.5 pf note 4 table 12-10. analog input specifications. note 1: this is the series resistance between the pad and the analog line in 2 cases 1. vbat 2.4v and the vmult peripheral is present on the circuit and enabled. 2. vbat 3.0v and the vmult peripheral is not present on the circuit. note 2: this is the series resistance in case vbat 2.8v and the peripheral vmult is not present on the circuit. note 3: this is the input capacitance seen on the pin when the pin is not connected to an analog line. this value is indicative only since it is product and package dependent. note 4: this is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin is connected to the same analog line. this value is i ndicative only since it is product and package dependent. 12.6 port b function capability the port b can be used for different functions impl emented by other peripherals. the description below is applicable only in so far the circuit contains these peripherals. when the counters are used to implement a pwm function (see the documentation of t he counters), the pb[0] and pb[1] terminals are used as outputs (pb[0] is used if cntpwm0 in regcntconfig1 is set to 1, pb[1] is used if cntpwm1 in regcntconfig1 is set to 1) and the pwm generated values override the values written in regpbout . however, pbdir(0) and pbdir(1) are not automatically overwritten and have to be set to 1. if output16k is set in regsysmisc , the frequency is output on pb[3]. th is overrides the value contained in pbout(3) . however, pbdir(3) must be set to 1. the frequency and duty cycle of the clock signal are given in figure 12-1. f max is the frequency of fastest clock present in the circuit. 1/16k 1/fmax figure 12-1. 16 khz output clock timing similarly, if outputckcpu is set in regsysmisc , the cpu frequency is output on pb[2]. this overrides the value contained in pbout(2) . however, pbdir(2) must be set to 1. 1/f2 1/f1 figure 12-2. cpu output clock timing.
? semtech 2006 www.semtech.com 12-6 xe8806a/xe8807a the timing of the cpu clock (figure 12- 2) depends on the selection of the cpusel bit in the regsysclock register and is given in table 12-11. f max is the frequency of fastest clock present in the circuit. note that the tolerance on the 32 khz depends on the selected clock source (see clock block documentation). cpusel f1 f2 0 f max /4 f max 1 f max 32 khz table 12-11. cpu clock timing parameters. pins pb[5] and pb[4] can be used for s1 and s0 of the usrt (see usrt documentation) when the usrtenable bit is set in regusrtctrl . the pb[5] and pb[4] then become open-drain. this overrides the values contained in pbopen(5:4) , pbout(5:4) and pbdir(5:4) . if there is no external pull-up resistor on these pins, internal pull-ups should be selected by setting pbpullup(5:4) . when s0 is an output, the pin pb[4] takes the value of usrts0 in regusrts0 . when s1 is an output, the pin pb[5] takes the value of usrts1 in regusrts1 . pins pb[6] and pb[7] can be used by t he uart (see uart documentation). when uartentx in reguartctrl is set to 1, pb[6] is used as output signal tx. when uartenrx in reguartctrl is set to 1, pb[7] is used as input signal rx. this overrides the values contained in pbout(7:6) and pbdir(7:6) . 12.7 port b digital capabilities 12.7.1 port b digital configuration the direction of each bit within port b (input only or input/output) can be individually set using the regpbdir register. if pbdir[x] = 1, both the input and output buffer are active on the corresponding port b. if pbdir[x] = 0, the corresponding port b pin is an input only and the output buffer is in high impedance. after reset (nresetpconf) port b is in input only mode (pbdir[x] are reset to 0). the input values of port b are available in regpbin (read only). reading is always direct - there is no debounce function in port b. in case of possible noise on inpu t signals, a software debouncer with polling or an external hardware filter have to be realized. the input buffer is also active when the port is defined as output and the effective value on the pin can be read back. data stored in regpbout are outputted at port b if pbdir[x] is 1. the default values after reset is low (0). when a pin is in output mode ( pbdir[x] is set to 1), the output can be a conventional cmos (push-pull) or a n- channel open-drain, driving the output only low. by default, after reset (nresetpconf) the pbopen[x] in regpbopen is cleared to 0 (push-pull). if pbopen[x] in regpbopen is set to 1 then the internal p transistor in the output buffer is electrically removed and the output can only be driven low ( pbout[x] =0). when pbout[x] =1, the pin is high impedance. the internal pull-up or an ex ternal pull-up resistor can be used to drive to pin high. note: because the p transistor actually exists (this is not a real open-drain output) the pull-up range is limited to vdd + 0.2v (avoid forward bias the p transistor / diode). each bit can be set individually for pull-up or not using register regpbpullup . input is pulled up when its corresponding bit in this register is set to 1. default stat us after (nresetpconf) is 1, which means with pull up. to limit power consumption, pull-up resist ors are only enabled when the associated pin is either a digital input or an n- channel open-drain output with the pad set to 1. in the other cases (push-pull output or open-drain output driven low), the pull up resistors are disabled independent of the value in regpbpullup . after power-on reset, the port b is configured as an input port with pull-up. during power-on reset (see reset block documentation) however, the pin pb[1] is pulled down in stead of pulled up. once the power-on reset completed, the pin pb[1] is pulled up, exactly as the other port b pins.
? semtech 2006 www.semtech.com 12-7 xe8806a/xe8807a the input buffer is always active, except in analog mode. this means that the port b input should be a valid digital value at all times unless the pin is set in analog mode. violating this rule may lead to high power consumption. 12.7.2 port b digital function specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.5 pf note 1 note 1: this value is indicative only since it depends on the package. table 12-12. digital port specification 12.8 low power comparators if the low power comparator (cmpd) peri pheral is present in the circuit, the si gnals on the pins pb[7:4] can be used as inputs for these low power comparators. although the comparators are functional independent of the port b configuration, it is recommended to set the pins that ar e used for the cmpd in analog mode without selecting any analog lines. this to avoid high power consumption in the digital input buffer when analog or slowly varying digital signals are applied.
? semtech 2006 www.semtech.com 13-1 xe8806a/xe8807a 13. port d 13.1 features 13-2 13.2 overview 13-2 13.3 register map 13-2 13.4 port d (pd) operation 13-3 13.5 port d electrical specification 13-4
? semtech 2006 www.semtech.com 13-2 xe8806a/xe8807a 13.1 features ? input / output port, 8 bits wide ? each bit can be set individually for input or output ? pull-ups are available in input mode ? snap-to-rail option in input mode 13.2 overview port d (pd) is a general purpose 8 bit input/output digital port. figure 13-1 shows its structure. figure 13-1 : structure of portd 13.3 register map there are four registers in the port d (pd), namely regpdin , regpdout , regpddir and regpdpullup . table 13-2 to table 13-5 show the mapping of control bits and functionality of these registers. register name regpdin regpdout regpddir regpdpullup table 13-1: pd registers regpdpullup[3:0] regpdpullup[7:4] logic vbat vss regpdin regpdout regpddir 4 4 8 8 8
? semtech 2006 www.semtech.com 13-3 xe8806a/xe8807a pos. regpdin rw reset description 7:0 pdin[7:0] r - pad pd[7:0] input value table 13-2: regpdin pos. regpdout rw reset description 7:0 pdout[7:0] r w 0 nresetpconf pad pd[7:0] output value table 13-3: regpdout pos. regpddir rw reset description 7:0 pddir[7:0] r w 0 nresetpconf pad pd[7:0] direction (0=input) table 13-4: regpddir pos. regpdpullup rw reset description 7 pdsnaptorail[3] r w 1 nresetpconf snap-to-rail for pad pd[7] and pd[6] (1=active) 6 pdsnaptorail[2] r w 1 nresetpconf snap-to-rail for pad pd[5] and pd[4] (1=active) 5 pdsnaptorail[1] r w 1 nresetpconf snap-to-rail for pad pd[3] and pd[2] (1=active) 4 pdsnaptorail[0] r w 1 nresetpconf snap-to-rail for pad pd[1] and pd[0] (1=active) 3 pdpullup[3] r w 1 nresetpconf pullup for pad pd[7] and pd[6] (1=active) 2 pdpullup[2] r w 1 nresetpconf pullup for pad pd[5] and pd[4] (1=active) 1 pdpullup[1] r w 1 nresetpconf pullup for pad pd[3] and pd[2] (1=active) 0 pdpullup[0] r w 1 nresetpconf pullup for pad pd[1] and pd[0] (1=active) table 13-5: regpdpullup 13.4 port d (pd) operation the direction of each pin of port d (input or in put/output) can be individually set by using the regpddir register. if pddir[x] = 1, the output buffer on the corresponding port d pi n is enabled. after reset, port d is in input only mode ( pddir[x] are reset to 0). the input buffer is always enabled independently from the regpddir contents. output data: data are stored in regpdout prior to output at port d. input data: the status of port d is available in regpdin (read only). reading is always direct - there is no digital debounce function associated with port d. in case of possible noi se on input signals, a software debouncer or an external filter must be realised. pull-up/snap to rail: when configured as an input ( pddir[x] =0), pull-ups are available on every pin. the pull-up function of the pins is controlled two by two by the pdpullup and pdsnaptorail bits in the register regpdpullup . when a bit
? semtech 2006 www.semtech.com 13-4 xe8806a/xe8807a pdpullup[x] is 0, the pull-ups on the pins pd[2x] and pd[2x+1] are disabled. when a bit pdpullup[x] is set to 1 and the bit pdsnaptorail[x] is set to 0, the pull-up resistor is co nnected to the pins pd[2x] and pd[2x+1]. when both pdpullup[x] and pdsnaptorail[x] are 1, the snap-to-rail function is acti ve on the pins pd[2x] and pd[2x+1]. the snap-to-rail function connects a pullup or pulldown resi stor to the input pin depending on the value forced on the input pin. this function can be used for instance when the input port is connected to a tristate bus. when the bus is floating, the pullup or pulldown maintains the bus in the last low impedance state before it became floating until another low impedance output is driv ing the bus. it also reduces the power consumption with respect to a classic pullup since it selects the pullup or pulldown resi stor so that it confirms the detected input state. the function is summarised in the table below as a function of the different register settings. pddir[2x(+1)] pdpullup[x] pdsnaptorail[x] (last) externally forced pd[2x(+1)] value pd[2x(+1)] pull resistor 1 x x x not connected 0 0 x x not connected 0 1 0 x pullup 0 1 1 0 pulldown 0 1 1 1 pullup table 13-6: snap-to-rail and pullup function at power-on reset, port d is configured as an input port with all pull-ups active. 13.5 port d electri cal specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.0 pf note 1 note 1: this value is indicative only since it depends on the package. table 13-7. port d electrical specification
? semtech 2006 www.semtec h.com 14-1 xe8806a/xe8807a 14. rf interface (bitjockey tm ) 14.1 introduction 14-2 14.2 features 14-2 14.3 general overview 14-2 14.4 register map 14-3 14.5 interrupts 14-5 14.6 external connections 14-5 14.7 supported pcm codes 14-5 14.8 reception mode: detailed description 14-6 14.8.1 input data filter and bit synchronization 14-7 14.8.1.1 nrz code 14-7 14.8.1.2 bi-phase and miller code 14-7 14.8.2 start sequence detection or message synchronization 14-7 14.8.2.1 no start sequence detection 14-8 14.8.2.2 ?protocol? start detection 14-8 14.8.2.3 ?external? start detection 14-8 14.8.2.4 ?pattern? start detection 14-9 14.8.3 pcm decoding 14-10 14.8.4 reception fifo 14-10 14.8.5 reception interrupts 14-11 14.9 transmission mode 14-11 14.9.1 transmission fifo 14-11 14.9.2 transmission interrupts 14-11 14.9.3 transmission encoding 14-11 14.9.4 transmission synchronization clock 14-12 14.10 baud rate selection 14-13 14.11 specifications 14-14 14.12 application hints 14-14 14.12.1 using the rf interface with the xe1201a 14-14 14.12.1.1 microcontroller ? transceiver connections 14-14 14.12.1.2 reception mode using nrz codi ng and the xe1201a bit synchronizer 14-15 14.12.1.3 reception mode using manchester coding 14-17 14.12.1.4 transmission mode using nrz coding 14-18 14.12.1.5 transmission mode using miller code 14-19 14.12.2 using the rf interface with the xe1202 14-20 14.12.2.1 microcontroller ? transceiver connections 14-20 14.12.2.2 microcontroller clock source der ived from xe1202 crystal oscillator 14-21 14.12.2.3 reception mode using nrz coding and the xe1202 bit and message synchronizer 14-22 14.12.2.4 reception mode using manchester coding 14-23 14.12.2.5 transmission mode using nrz coding 14-25 14.12.2.6 transmission mode using manchester code 14-26
? semtech 2006 www.semt ech.com 14-2 xe8806a/xe8807a 14.1 introduction this block is a pcm bit stream encoder / decoder or rf receiver / transmitter interface. in a normal microcontroller, the bits and low level coding of the rf pr otocol are done by software. this is a very tedious and cpu time consuming task since the processor has to handle bi t by bit as they are rece ived or as they have to be transmitted. this block simplifies the handling of the lo w level data handling for wireless data transmission systems very much in a similar way an uart inte rface does for wired transmission systems. 14.2 features ? two functions : receiver and transmitter (half duplex) ? internal baud rate generator for all the standard baud rates ? decode / encode 3 main pcm codes (nrz , bi-phase and miller), can be bypassed ? buffered input / output data (fifo) ? 4 interrupt sources ? internal or external bit synchronization ? internal or external start sequence detection 14.3 general overview the rf interface block is a bit stream receiver / trans mitter for wireless transmission. it can be used with xemics? or third party rf transceiver circuits. start detection pcm decoder reception input stream prescaler transmission control enable/bypass enable/bypass clock baudrate / pcm type clock clock output stream external clock data data pcm type ctrl sig. status. ctrl sig. status. pcm encoder / decoder clock interrupts shift register shift register match rfif0 rfif1 rfif2 rfif3 filter pcm encoder enable/bypass fifo fifo figure 14-1 : pcm encoder / decoder structure
? semtech 2006 www.semt ech.com 14-3 xe8806a/xe8807a the reception block consists of: ? the ?filter?. the input data are filtered depending on the selected baud rate. the block extracts the bit synchronization clock. when an external bit synchroni zation clock is used, the filter is bypassed. ? the ?start detection? block. this block detects a programmable start sequence and therefore synchronizes at the message start. the interface ignores incoming mess ages until the start sequence is detected. this block can be bypassed or an external message synchroniza tion signal can be used (match in figure 14-1). ? the ?pcm decoder? which decodes the 3 main types of pcm waveforms ( i.e. nrz, bi-phase, miller). this block can be bypassed. ? the ?shift register? and the fifo, that do the serial to parallel conversion and memorize the input data. the transmission block consists of: ? the fifo and the ?shift register? which store t he data and do the parallel to serial conversion. ? the ?encoder? which encodes the serial data into the chosen pcm type. this block can be bypassed. the prescaler generates the clock signals needed for the rec eption and transmission depending on the selected baud rate and pcm code type. 14.4 register map register name regrfifcmd1 regrfifcmd2 regrfifcmd3 regrfiftx regrfiftxsta regrfifrx regrfifrxsta regrfifrxspat table 14-1: rfif registers pos. regrfifcmd1 rw reset description 7-6 unused - - - 5-4 rfifbrcoarse(1:0) r/w 00 nresetglobal select baud rate (coarse selection) 3-0 rfifbrfine(3:0) r/w 0000 nresetglobal select baud rate (fine selection) table 14-2: regrfifcmd1 pos. regrfifcmd2 rw reset description 7-6 rfifenstart(1:0) r/w 00 nresetglobal start detection mode in rx mode (see page 14-8) 5 rfifencod r/w 0 nresetglobal ?1? enables decoder (rx) / encoder (tx) 4 rfifrxclock r/w 0 nresetglobal ?1? enables external clock input (rx) 3 rfiftxclock r/w 0 nresetglobal ?1? enables external clock output (tx) 2-0 rfifpcm(2:0) r/w 000 nresetgl obal select pcm type (see page 14-6) table 14-3: regrfifcmd2
? semtech 2006 www.semt ech.com 14-4 xe8806a/xe8807a pos. regrfifcmd3 rw reset description 7-5 rfifrxirqen r/w 000 nresetglobal ?1? enable the rx irq sources (see page 14-11) 4-2 rfifrxirqmem r/c1 000 nresetgl obal rx irq status (see page 14-11) 1 rfifenrx r/w 0 nresetpconf ?1? enable rfif reception mode 0 rfifentx r/w 0 nresetpconf ?1? enable rfif transmission mode table 14-4: regrfifcmd3 pos. regrfiftx rw reset description 7-0 rfiftx w 00000000 nresetglobal data to be sent fifo, depth = 4 table 14-5: regrfiftx pos. regrfiftxsta rw reset description 7-4 - - - - 3 rfiftxfifooverrun r/c1 0 nresetglobal tx fifo overrun error. write: clear fifo 2 rfiftxfifofull r 0 nresetglobal tx fifo full 1 rfiftxfifoempty r 1 nresetglobal tx fifo empty [irq] 0 rfiftxstopped r 0 nresetglobal tx fifo + tx shift register empty: stopped table 14-6: regrfiftxsta pos. regrfifrx rw reset description 7-0 rfifrx r 00000000 nresetglobal received data fifo, depth = 4 table 14-7: regrfifrx pos. regrfifrxsta rw reset description 7-5 - - - - 4 rfifrxfifooverrun r/c1 0 nresetglobal rx fifo overrun error. write: clear fifo 3 rfifrxfifofull r 0 nresetglobal rx fifo full [irq] 2 rfifrxstartdet r/c1 0 nresetgl obal start stream detected [irq] 1 rfifrxbusy r 0 nresetgl obal rfif busy receiving 0 rfifrxready = rfifrxnotempty r 0 nresetglobal regrfifrx contains at least one byte to read. cleared when reading regrfifrx .[irq] table 14-8: regrfifrxsta pos. regrfifrxspat rw reset description 7-0 rfifrxspat r/w 00000000 nresetglobal programmable start pattern table 14-9: regrfifrxspat
? semtech 2006 www.semt ech.com 14-5 xe8806a/xe8807a 14.5 interrupts two interrupt lines exist: one for t he transmitter and one for the receiver. interrupt source irq_rfif_rx irq_rfif_tx table 14-10: interrupts 14.6 external connections the interface uses 4 i/o pins. the use of these pins depends on the set up of the interface. table 14-11 shows the possible use of these pins. in receive mode, the pin rfif0 is the receiver data stream input. if the exte rnal bit synchronization clock mode is selected, the rfif1 pin should be connect ed to the bit synchronizer clock of the receiver. if the receiver has a message synchronization signal, it can be connected to rfif2. in transmitter mode, the transmitter data pin has to be connected to rfif3. a bit synchronization clock can be generated on rfif2. rfif0 rfif1 rfif2 rfif3 receive mode data in clock match - transmit mode - - clock data out table 14-11 : pad management in case the rfif pins are multiplexed on a parallel digital i/o port, the interface overwrites all four digital pins as soon as the receive mode or transmitter mode of the interface are enabled (bit rfifenrx or rfifentx in register regrfifcmd3 is set at 1). unused pins are configured as inputs with a weak pull-up or pull-down. these pins may remain floating or may be driven externally. no external pu ll-ups or pull-downs are required. 14.7 supported pcm codes seven different pcm codes are suppor ted by the interface. they ar e illustrated in the figure below. nrz code : in this format one message bit is represented by one chip (i.e. the distance between two dotted lines in figure 14-2). the coding does not include clock info rmation. the bit sampling clock information has to be extracted from the message preamble. bi-phase code or manchester code : in this format one message bit is represented by two chips. this code contains clock information. delay modulation or miller code : in this format one message bit is represented by two chips . this code contains clock information. the interface can receive and transmit coded or uncoded messages. the coding/decoding function is enabled/disabled using the bit rfifencod (1 = enable) in the register regrfifcmd2 .
? semtech 2006 www.semt ech.com 14-6 xe8806a/xe8807a 0 space nrz - le ve l bi-phase - level delay modulation / miller 1 mark 1 mark 0 space 0 space 1 mark 1 mark types of pcm codes nrz - mark nrz - space bi-phase - mark bi-phase - space sampling = 8 x baudrate sampling = 16 x baudrate figure 14-2 : supported pcm codes the pcm code type is selected using the rfifpcm[2:0] control word in the register regrfifcmd2 . the selection control bits are given in table 14-12. nrz bi-phase pcm codes level mark space level mark space miller rfifpcm[2:0] 000 001 010 011 100 101 11x table 14-12: pcm code selection 14.8 reception mode: detailed description the interface is configured in reception mode by setting the bit rfifenrx (1 = enable) and clearing the bit rfifentx (0 = disable transmission) in the register regrfifcmd3 . the input data stream coming from the receiv er has to be connected to the rfif0 pin.
? semtech 2006 www.semt ech.com 14-7 xe8806a/xe8807a 14.8.1 input data filter and bit synchronization 14.8.1.1 nrz code when the nrz codes are used, the bit synchronization cl ock should be extracted from the preamble since the coding itself may not contain clock information. the i nput data filter has to be used (see description below in section 14.8.1.2) to extract the bit synchronization clock. the bit rfifrxclock in register regrfifcmd2 is to be cleared to 0. if the input data stream contains long per iods without transitions, the internally generated bit synchronization clock could slip with respect to the bit rate resulting in transmission errors (see also specification in chapter 14.11). tests have shown a very robust behav ior with the internal bit synchronizer though. an external bit synchronization clock can be used. this cl ock has to be delivered on the pin rfif1. the bit stream on rfif0 is then sampled on detection of the rising edge of the clock on the rfif1 pin. this function has to be enabled by setting bit rfifrxclock in register regrfifcmd2 to 1. selecting this func tion bypasses the input filter. in practice, it was found that the sync hronization was more reliable with the in ternal synchronization filter than with the external bit clock. 14.8.1.2 bi-phase and miller code the bi-phase and miller code include clock information and no external bit synchronization clock is needed. the input data filter is used to filter the noise on the input data. the filter sample s the input data at 16 times the selected baud rate and performs the following majority function on 8 successive samples: if (number of ?1? in the last 8 samples >= 6) data = 1 if (number of ?1? in the last 8 samples <= 2) data = 0 else data = former data the filter has some hysteresis since the output does not change when the number of 1?s is between 2 and 6. the input filter is always selected for the bi-phas e and miller coding independent from the value of the bit rfifrxclock in register regrfifcmd2 . 14.8.2 start sequence detection or message synchronization a full message is mainly co mposed of three parts: 1) a preamble or start sequence 2) the data itself 3) an optional stop sequence. a start sequence is necessary to indi cate the start of a new message. the interface supports the detection of several types of start sequences. the user c an chose between these start sequence detection modes using the bits rfifenstart[1:0] in regrfifcmd2 as shown in table 14-13. the actual implementation of the detection mode differs depending on the selected pcm coding and is described below. a start sequence detection will set the bit rfifrxstartdet in the register regrfifrxsta and generate an interrupt on the irq_rfif_rx line. the contents of the reception fifo is reset. the dat a of the preceding message that were not yet read at the occurrence of a new start sequence are los t. the first bit in the fifo is the first valid bit decoded after the detected start sequence. the bit rfifrxstartdet has to be cleared by software by writing a 1 to the bit.
? semtech 2006 www.semt ech.com 14-8 xe8806a/xe8807a start detection mode name rfifenstart[1:0] ?none? 00 ?protocol? 01 ?external? 10 ?pattern 8bits? 11 table 14-13. start detection mode selection 14.8.2.1 no start sequence detection in this case, the interface will not look for a start sequence. the incoming data stream will be decoded according to the selected pcm code and will be stored in the reception fifo as soon as the reception mode is enabled. the message start has to be detected by software. 14.8.2.2 ?protocol? start detection the nrz coding has no defined start sequence. selecting the ?protocol? start sequence in nrz has the same effect as no start detection. in the bi-phase or manchester code, any protocol violation is considered as a start sequence i.e. a 1-level or 0-level which is longer than the duration of a chip . an example is shown in figure 14-3. in the delay modulation or miller coding, any protocol violation is considered as a start sequence i.e. a 1-level or 0- level which is longer than the duration of 2 chips. figure 14-3 : start sequence type in bi-phase-level encoding 14.8.2.3 ?external? start detection an external start detection signal can be used. this si gnal should be connected to the pin rfif2. the falling edge of rfif2 (also called ?match?, see figure 14-1) indicates the first valid bit of the message. this edge has to occur during the first half of the first bit as shown in figur e 14-4. the minimal width of the pulse is half a bit. bi-phase - level 1 0100111110100010 110 0 1 start sequence 5 x '1' other start sequence 3 x '0' codes first valid bit first valid bit bit sequence
? semtech 2006 www.semt ech.com 14-9 xe8806a/xe8807a figure 14-4. timing of the external word synchronization signal 14.8.2.4 ?pattern? start detection the start sequence is defined by the pattern rfifrxspat[7:0] written in the register regfifrxspat . this pattern is compared to the incoming bit stream before decoding. this is shown in figure 14-5 and figure 14-6 where an identical input data bit stream and an identical pattern give the same start sequence detection independent from the decoded data. figure 14-5. pattern start detection in nrz-level for rfifrxspat[7:0]=10011111 nrz - level 1 0100111110100010 first bit in fifo decoded data rfif2 (match) nrz - level 1 0100111110100010 start sequence first bit in fifo rfifrxspat =10011111 decoded data
? semtech 2006 www.semt ech.com 14-10 xe8806a/xe8807a figure 14-6. pattern start detection in nrz-mark for rfifrxspat[7:0]=10011111 the start pattern can not be less than 8 bits since no bits can be set as ?don?t care?. 14.8.3 pcm decoding the interface can receive coded or uncoded messages. the coding/decoding function is enabled/disabled using the bit rfifencod (1 = enable) in the register regrfifcmd2 . the pcm code type is selected using the rfifpcm[2:0] control word in the register regrfifcmd2 . the selection control bits are given in table 14-12. nrz bi-phase pcm codes level mark space level mark space miller rfifpcm[2:0] 000 001 010 011 100 101 11x table 14-14: pcm code selection if the decoder detects invalid code s equences and the selected start detection mode is not the ?protocol ? mode ( rfifenstart[1:0] 01, see table 14-13), the decoder output generat es an equivalent number of random data bits. if the decoder is disabled ( rfifencod = 0), the meaning of the rfifpcm[2:0] changes: if the nrz coding is selected, the input bit stream is samp led at the selected bit rate. if the manc hester or miller coding is selected, the input stream is sampled at twice the data rate. this allows the decoding of the bit stream by software. 14.8.4 reception fifo the decoder output data are serially shifted in a shift register (see figure 14-1). the bit rfifrxbusy = 1 in regrfifrxsta indicates that new data are shifted in. when 8 new bits are present in the shift register, the byte is loaded in the fifo. the fifo has a depth of 4. the bit rfifrxready = 1 in regrfifrxsta indicates that at least 1 byte is pres ent in the fifo. the software can read the data in the fifo in regrfifrx . when the bit rfifrxfifofull is 1, the fifo is full and data should be read by the software before the next byte is receiv ed. if not, data will be lost and the bit rfifrxfifooverrun is set to 1. writing a 1 to this bit will clear the bit and the fifo contents. the detection of a new start sequence will also clear the rfifrxfifooverrun bit and the fifo contents. the first bit that is received can be found in the position rfifrx[0] , the second bit in the position rfifrx[1] and so on. nrz - mark 1 1110100001110011 start sequence first bit in fifo rfifrxspat =10011111 decoded data
? semtech 2006 www.semt ech.com 14-11 xe8806a/xe8807a 14.8.5 reception interrupts only one interrupt line is dedicated to the rf receiver in terface. the interrupt can be generated by three different sources however. the bits rfifrxirqen[2:0] in regrfifcmd3 allow the selection of the interrupt source(s) as shown in table 14-15. possible interrupt sources are the det ection of a message start, the shift of the first byte in the fifo after the fifo was cleared and fi nally when the fifo is full. the bits rfifrxirqmem[2:0] in regrfifcmd3 flag which interrupt source was active since thes e bits were last cleared. the interrupt flags are cleared by writing a 1. more than one interr upt source can be enabled at the same time. rfifrxirqen[2:0] rfifrxirqmem[2:0] interrupt source xx1 start sequence detection x1x a new byte is written to fifo 1xx fifo is full table 14-15. reception interrupt source selection the first interrupt allows easy synchronization to the message start. the second interrupt can be used if one wants to download the message one byte at a time. the thir d interrupt can be used if one wants to download the message 4 bytes at a time. 14.9 transmission mode the interface is configured in reception mode by setting the bit rfifentx (1 = enable) and clearing the bit rfifenrx (0 = disable reception) in the register regrfifcmd3 . when the transmission mode is switched off again, the transmission will stop when the transmission of the by te in the shift register is completed. the output data stream will be generated on the rfif3 pin. 14.9.1 transmission fifo data to be transmitted are written to t he fifo by writing to the register regrfiftx . these data are then loaded in the shift register which sends the data bit by bit to the encoder (figure 14-1). if the transmission fifo is full, the bit rfiftxfifofull in regrfiftxsta is set to 1. if the software continues to writ e data to the fifo while it is full, the flag rfiftxfifooverrun will be set to 1 and the data will be lost. the rfiftxfifooverrun flag is cleared by writing a 1 to it. this clears the contents of the trans mission fifo at the same time. when the last data byte present in the fifo is loaded in the shift register, the flag rfiftxfifoempty is set to 1. if the software does not write new data to the fifo and the shift register finished shi fting the last bit to the encoder, the bit rfiftxstopped is set to 1. the rfif3 pin remains in the last encoded state. the first bit sent is the bit rfiftx[0] , the second bit is rfiftx[1] and so on. 14.9.2 transmission interrupts only one interrupt source exists during the transmission: an interrupt can be generated at the moment the last byte of the fifo is transferred to the transmission shift regist er. it means that the fifo is empty and has to be refilled with data. the interrupt is enabled in the interrupt manager block. 14.9.3 transmission encoding the transmission encoder can be bypassed by clearing the bit rfifencod in register regrfifcmd2 . the bit stream on the rfif3 pin is then directly connect ed to the output of the shift register.
? semtech 2006 www.semt ech.com 14-12 xe8806a/xe8807a if rfifencod in register regrfifcmd2 is set to 1, the bit stream coming fr om the shift register is encoded first before sending it to the rfif3 pin. the ty pe of protocol is selected using the rfifpcm[2:0] control word in the register regrfifcmd2 . the selection control bits are given in table 14-14. nrz bi-phase/manchester pcm codes level mark space level mark space miller rfifpcm[2:0] 000 001 010 011 100 101 11x table 14-16: pcm code selection when the bit rfifencod is modified while a transmission is active, t he modification will take effect only when a new byte is loaded from the fifo into the shift register. while the encoder is enabled, it is not possible to send a prot ocol violation as a start pattern. if a protocol violation is used as a start sequence in t he manchester or miller protocol, the following sequence should be used: 1) wait until the transmission fifo is empty (which means the last byte of the preceding message is being coded and sent), 2) clear rfifencod , 3) write the uncoded start pattern to the transmission fifo 4) wait until the transmission fifo is empty (which m eans the last byte of the uncoded start pattern is being sent) 5) set rfifencod 6) write the message bytes to the fifo 7) back to 1. beware that in the case a protocol violation is used as a start sequence in manchester-level or miller coding, the used violation will depend on the value of the first bit of the message. as an example: if the manchester level coding is used and the first bit of the message is a 0 ( encoded 01), the start sequence needs to be a series of 1?s. if a series of 0?s would be used, the receiver would be unable to distinguish the leading 0 of the message from the start sequence. when the encoder is bypassed ( rfifencod = 0), bits rfifpcm[2:0] still have an influence on the output bit stream : when the nrz coding is chosen, the bits are shifted out at the selected bit rate. if the manchester or miller codes are selected however, the bits are shifted out at twice the data rate. this allows the use of two bits in the fifo to encode the bits by software. 14.9.4 transmission synchronization clock if required, a bit synchronization clock can be generated on the pin rfif2 if the data is uncoded or if the nrz coding is used (bits rfifencod and rfifpcm[2:0] in regrfifcmd2 ). to generate this clock, the bit rfiftxclock in regrfifcmd2 has to be set. the timing of the generated clock is shown in figure 14-7.
? semtech 2006 www.semt ech.com 14-13 xe8806a/xe8807a nrz - le ve l bi-phase - level output bitstream output bitstream output clock figure 14-7 : output clock in transmission mode 14.10 baud rate selection in order to have correct baud rates, the interface has to be fed with a stable and trimmed clock source. the clock source can be an external clock source or the rc o scillator. the precision of the baud rate will depend on the precision of the selected clock source. the choice betw een the rc oscillator and the external clock source is made with the bit enextclock in regsysclock . the precision of the obtained baud rate is directly proportional to the frequency deviation of the used clock source. the bits rfifbrcoarse[1:0] and rfifbrfine[3:0] in regrfifcmd1 are used to select the appropriate baud rate. several rc division factors are available. the expression of the baud rate is the following: 16 * coarse fine f baudrate rcext ? = with: rcext f : rc frequency or the half the external clock frequency. fine and coarse: the division factors selected by rfifbrcoarse and rfifbrfine . note that the baud rate is the rate at which the chips are transmitted and is twice t he bit rate in manchester and miller coding since these codes use tw o chips per bit (see chapter 14.7). rfifbrfine[3:0] fine 0000 1 0001 2 0010 3 0011 4 ... ... 1101 14 1110 15 1111 16 table 14-17 : effect of rfifbrfine[3:0]
? semtech 2006 www.semt ech.com 14-14 xe8806a/xe8807a rfifbrcoarse[1:0] coarse 00 1 01 4 10 8 11 16 table 14-18 : effect of rfifbrcoarse[1:0] even if the external bit synchronizer is used, the baud rate should be set correctly. 14.11 specifications if a frequency difference exists between the transmitter and the receiver, the receiver may be unable to decode the received messages correctly. this is especially the case if no protocol or if the nrz protocols are used without an external bit synchronization clock si nce these signals do not contain clo ck information. manchester and miller coding are more robust since the decoder can resynchronize on the code itself. the estimated maximal tolerated frequency difference between the transmitter and the rf interface are the following (theoretical values): mode maximal tolerated ? f=f rx -f tx nrz, no external clock to receive 10 identical and consecutive bits: 4% nrz, with external clock -50%/+100% manchester -17%/+11% miller -9%/+8% table 14-19 : frequency difference tolerance in nrz without external bit synchroni zer, it should be noted that the tolera ted frequency deviation is larger if the number of consecutive identical bits is lower than 10. 14.12 application hints standard api functions to drive the xe1200 series are giv en in the tn8000.18. using these api functions will allow you to set-up a transmission betw een two systems very quickly. below, you will find some examples on how to set- up the rf circuits and the rf interface (bitjockey tm ). 14.12.1 using the rf interface with the xe1201a this chapter gives some examples on how the rf in terface can be used with the xe1201a circuit. it does not describe all possibilities but sele cts some representative cases. 14.12.1.1 microcontroller ? transceiver connections for the external components required to operate the xe1201a, please refer to the xe1201a datasheet. the connections between the xe8000 microcontroller and the xe1201a are shown in figure 14-8. the transmission data pins are connected between the rf inte rface of the microcontroller and the transceiver. the configuration lines of the xe1201a can be driven by pins of a parallel port. the 3-wire configuration data bus of the xe1201a is used to set-up the circuit by writing in the registers a, b and c. the interface can be driven by a hardware spi or by a software spi on a parallel port. pins of the rf interface rfif0 to rfif3 that are not used may remain floating.
? semtech 2006 www.semt ech.com 14-15 xe8806a/xe8807a if the xe1201a is used as a transmitte r only, the connections rfif0 ? rxd and rfif1 ? clkd are not required. the rxtx pin of the xe1201a can be permanently connected to the ground. rfif0 and rfif1 may remain floating. if the xe1201a is used as a receiver only, the connection rfif3 ? txd is not required. the pin txd and the pin txrx can be permanently connected to vdd. if the bit synchronizer in t he xe1201a is not used, the connection rfif1 ? clkd is not required. if the xe1201a transmitter is permanently enabled, t he pin en can be permanently connected to vdd. this documentation shows how to set-up the data tr ansmission between the microc ontroller and the xe1201a. for detailed information on the xe1201a functi onality, external components, serial interface protocol and register set- up, please refer to the xe1201a datasheet. rfif0 rfif1 rfif2 rfif3 txd rxd clkd xe1201 [clock] data xe8000 en rxtx data de sc sd rf interface parallel port hardware or software spi ss sck mosi register a register b register c regrfifcmd2 regrfifcmd3 regrfiftx regrfiftxsta regrfifrx regrfifrxsta regrfifrxspat re g rfifcmd1 miso figure 14-8 : configuration of the connections between the microcontroller and xe1201a 14.12.1.2 reception mode using nrz c oding and the xe1201a bit synchronizer the protocol of the messages received is nrz leve l. the start sequence of the message is a 11010111 pattern and the message length after the start sequence is 8 bytes. t he messages are sent at a data rate of 16 kbit/s. the following paragraphs will show how to set-up the xe1201a, how to set-up the rf interface and how to handle the received data.
? semtech 2006 www.semt ech.com 14-16 xe8806a/xe8807a 14.12.1.2.1 xe1201a set-up to set the xe1201a in reception mode, set the pin en to 1 and the pin rxtx to 1. the data rate of the xe1201a by default is 16kbit/s and the bit synchronizer is enabled by default. this means that the data registers of the xe1201a can remain in the default settings shown in tabl e 14-20. the serial interface connections of figure 14-8 are therefore not required. register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register a 0 0 0 0 0 0 0 0 0 1 0 0 0 0 register b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register c 0 1 0 1 0 1 0 0 1 0 0 0 0 0 table 14-20. xe1201a default register set-up (see xe1201a datasheet for bit explanation) 14.12.1.2.2 rf interface set-up set-up the rf interface of the microcontroller circuit as a receiver ( rfifenrx = 1 and rfifentx = 0). assume that the rc clock frequency used in the microcontroller is 1.0 mhz. to select the correct baud rate of 16 kbit/s according to the equation in chapter 14.10, fine*coarse =1.0e06/(16*16e3)=3.9. this can be approximated at 4 (see specification in table 14-19). this can be done by setting rfifbrcoarse = 01 and rfifbrfine = 0000. the external bit synchronization clock is switched off by setting the bit rfifrxclock = 0. the decoder is enabled and set to nrz level decoding by setting rfifencod = 1 and rfifpcm = 000. the start pattern detection is enabled by setting rfifenstart = 11 and writing 11010111 to rfifrxspat . the start sequence detection interrupt is enabled by setting rfifrxirqen = 001. the set-up of the interface is summarized in the table 14-21. register contents regrfifcmd1 00010000 regrfifcmd2 11100000 regrfifcmd3 00100010 regrfifrxspat 11010111 table 14-21. rf interface set-up 14.12.1.2.3 data reception in order to handle the received data by interrupt, enable the rf interface reception interrupt in the interrupt handler of the circuit. data received before the first start pattern detection after t he enabling of the interface are not relevant since we are not yet synchronized to the messages. since the star t detection interrupt has been enabled, nothing has to be done until the interrupt occurs. when the first interrupt occurs, we are synchronized to t he messages. in order to read data in an efficient way, the interrupt source is modified and set to ?rx fifo full? by writing 100 to rfifrxirqen . once this is done, we can wait for the next interrupt to download the received message. at each new interrupt, we can now read 4 bytes of the received message by reading the register regrfifrx 4 consecutive times. the interrupt s hould be served before the next byte is received since otherwise data may be
? semtech 2006 www.semt ech.com 14-17 xe8806a/xe8807a lost by lack of space in the fifo (overrun error which sets the flag rfifrxfifooverrun ) or because the start sequence of the next message is detected which resets the reception fifo. when the complete message is received, the st art sequence detection interrupt may be enabled again ( rfifrxirqen = 001) and the sequence starts all over again. 14.12.1.3 reception mode using manchester coding the protocol of the messages received is manchester mark. the start sequence of the message is protocol violation. the messages are sent at a data rate of 20 kbit/s (40 kbaud/s in manchester code). the following paragraphs will show how to set-up the xe1201a, how to set-up the rf interface and how to handle the received data. 14.12.1.3.1 xe1201a set-up to set the xe1201a in reception mode, set the pin en to 1 and the pin rxtx to 1. the bit synchronizer of the xe1201a is not used since the rf interf ace automatically synchronizes to the bit rate. this means that the data registers of the xe1201a can remain in the default settings shown in table 14-20. however, in order to reduce the power consumption, the xe1201a bit sy nchronizer can be switched off by writ ing the bits a(9:6) = 0101 as shown in table 14-22. register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register a 0 0 0 0 0 1 0 1 0 1 0 0 0 0 register b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register c 0 1 0 1 0 1 0 0 1 0 0 0 0 0 table 14-22. xe1201a register set-up (see xe1201a datasheet for bit explanation) 14.12.1.3.2 rf interface set-up set-up the rf interface of the microcontroller circuit as a receiver ( rfifenrx = 1 and rfifentx = 0). assume that the rc clock frequency used in the microcontroller is 2.0 mhz. to select the correct baud rate of 20 kbit/s according to the equation in chapter 14.10 (attention: the baud rate is twice the bit rate in manchester code), fine*coarse =2.0e06/(16*40e3)=3.12. we can approximate this at 3, which is close enough (see specification in table 14-19). this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 0010. the external bit synchronization clock is switched off by clearing the bit rfifrxclock = 0. the decoder is enabled and set to manchester mark decoding by setting rfifencod = 1 and rfifpcm = 100. the start detection by protocol violation is enabled by setting rfifenstart = 01. the start sequence detection interrupt is enabled by setting rfifrxirqen = 001. the set-up of the interface is summarized in the table 14-23. register contents regrfifcmd1 00000010 regrfifcmd2 10100100 regrfifcmd3 00100010 table 14-23. rf interface set-up
? semtech 2006 www.semt ech.com 14-18 xe8806a/xe8807a 14.12.1.3.3 data reception in order to handle the received data by interrupt, enable the rf interface reception interrupt in the interrupt handler of the circuit. data received before the first start pattern detection after t he enabling of the interface are not relevant since we are not yet synchronized to the messages. sine the start detection interrupt has been enabled, nothing has to be done until the interrupt occurs. when the first interrupt occurs, we are synchronized to t he messages. in order to read data in an efficient way, the interrupt source is modified and set to ?rx fifo full? by writing 100 to rfifrxirqen . once this is done, we can wait for the next interrupt to download the received message. at each new interrupt, we can now read 4 bytes of the received message by reading the register regrfifrx 4 consecutive times. the interrupt s hould be served before the next byte is received since otherwise data may be lost by lack of space in the fifo (overrun error which sets the flag rfifrxfifooverrun ) or because the start sequence of the next message is detected which resets the reception fifo. when the complete message is received, the st art sequence detection interrupt may be enabled again ( rfifrxirqen = 001) and the sequence starts all over again. 14.12.1.4 transmission mode using nrz coding the messages have to be sent encoded with nrz space. the start sequence of the message is 4 bytes of ?01010101?. the messages are sent at a data rate of 64 kbit/s and the modulator frequency deviation is 125khz and the output power is ?5dbm. the following paragraphs will show how to set-up the xe 1201a, how to set-up the rf interface and how to handle the transmission data. 14.12.1.4.1 xe1201a set-up to set the xe1201a in transmission mode, set the pin en to 1 and the pin rxtx to 0. the modulator deviation frequency is 125khz by default and the output power is ?5dbm by default, so there is no need to modify the registers of the xe1201a. 14.12.1.4.2 rf interface set-up set-up the rf interface of the micr ocontroller circuit as a transmitter ( rfifenrx = 0 and rfifentx = 1). assume that the rc clock frequency used in the microcontroller is 1.0 mhz. to select the correct baud rate of 64 kbit/s according to the equation in chapter 14.10, fine*coarse =1.0e06/(16*64e3)=0.98. we can approximate this at 1, which is close enough (see specification in table 14-19). this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 0000. the external bit synchronization clock is switched off by clearing the bit rfiftxclock = 0. the encoder is enabled and set to nrz space encoding by setting rfifencod = 1 and rfifpcm = 010. the set-up of the interface is summarized in the table 14-24. register contents regrfifcmd1 00000000 regrfifcmd2 00100010 regrfifcmd3 00000001 table 14-24. rf interface set-up
? semtech 2006 www.semt ech.com 14-19 xe8806a/xe8807a 14.12.1.4.3 data transmission to handle the transmission data by interrupt, enable the rf in terface transmission interrupt in the interrupt handler of the circuit. we need to send the start sequence (preamble) first. the start sequence is defined as 4 bytes of ?01010101?. since the nrz space encoder is enabled, four byte s of ?00000000? should be written to the register regrfiftx . after encoding, this will correspond to 4 bytes of ?01010101? . the fifo is now full, and we can wait for the interrupt, which will indicate that the fifo is empty. at occurrence of the interrupt, 4 bytes of the message can be written to the fifo until all message bytes are sent. 14.12.1.5 transmission mode using miller code the messages have to be encoded using the miller code. the start sequence of the message is a protocol violation. the messages are sent at a data rate of 5 kbit/s (or 10 kbaud/s in miller code) and the modulator frequency deviation is 25khz and the output power is +5dbm. the following paragraphs will show how to set-up the xe 1201a, how to set-up the rf interface and how to handle the transmission data. 14.12.1.5.1 xe1201a set-up to set the xe1201a in transmission mode, set the pin en to 1 and the pin rxtx to 0. the modulator deviation frequency is set to 23.4khz by writing c(6:0) = 0000110. t he output power is set to +5dbm by writing c(13:12) = 11. all other values remain default. the resulti ng register values are shown in table 14-25. register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register a 0 0 0 0 0 0 0 0 0 1 0 0 0 0 register b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register c 1 1 0 1 0 1 0 0 0 0 0 1 1 0 table 14-25. xe1201a register set-up (see xe1201a datasheet for bit explanation) 14.12.1.5.2 rf interface set-up set-up the rf interface of the micr ocontroller circuit as a transmitter ( rfifenrx = 0 and rfifentx = 1). assume that the rc clock frequency used in the microcontroller is 2.0 mhz. to select the correct baud rate of 5 kbit/s according to the equation in chapter 14.10 (attention: the baud rate is twice the bit rate in the miller code), fine*coarse =2.0e06/(16*10e3)=12.5. we can approxim ate this at 12, which gives us a data rate of 5.2 kbit/s. this can be done by setting rfifbrcoarse = 01 and rfifbrfine = 0010. if a data rate closer to the 5kbit/s target, the rc oscillator frequency could be slightly increased to 1.04 mhz which gives fine*coarse =13. the external bit synchronization clock is switched off by clearing the bit rfiftxclock = 0. the encoder is enabled and set to miller encoding by setting rfifencod = 1 and rfifpcm = 111. the set-up of the interface is summarized in table 14-26. register contents regrfifcmd1 00010010 regrfifcmd2 00100111 regrfifcmd3 00000001 table 14-26. rf interface set-up
? semtech 2006 www.semt ech.com 14-20 xe8806a/xe8807a 14.12.1.5.3 data transmission to handle the transmission data by interrupt, enable the rf in terface transmission interrupt in the interrupt handler of the circuit. we need to send the start sequence first. t he start sequence is defined as a protoc ol violation. to send a protocol violation, the encoder has to be disabled by clearing rfifencod = 0. we then can write for instance ?00000000? to rfiftx . at occurrence of the interrupt, the start sequence was transfe rred to the shift register and the fifo is empty. the encoder is to be enabled by setting rfifencod = 1. we do not need to wait until the start sequence transmission is completed, since the modification of the bit rfifencod is taken into account only at the transfer of the next byte from the fifo to the transmission shift register. t he first 4 bytes of the message can then be written to rfiftx . at each occurrence of the interrupt, 4 bytes of the mess age can be written to the fifo until the end of the message is reached. the whole operation star ts over again for the next message. 14.12.2 using the rf interface with the xe1202a this chapter gives some examples on how the rf in terface can be used with the xe1202a circuit. it does not describe all possibilities but sele cts some representative cases. 14.12.2.1 microcontroller ? transceiver connections for the external components required to operate the xe1202a, please refer to the xe1202a datasheet. the connections between the xe8000 microcontroller and t he xe1202 are shown in figure 14-9. the transmission data are connected between the rf interf ace of the microcontroller and the tran sceiver. the configuration lines of the xe1202a can be driven by pins of a parallel port. the 3- wire configuration data bus of the xe1202a is used to set-up the circuit by writing in t he registers rtparam, fsparam, adparam and pattern. the interface can be driven by a hardware spi or by a software spi on a parallel port. pins of the rf interface rfif0 to rfif3 that are not used may remain floating. if the xe1202a is used as a transmitter only, the c onnections rfif0 ? rxd, rfif1 ? clkd and rfif2 ? pattern are not required. if the xe1202a is used as a receiver only, the connection rfif 3 ? txd is not required. if the bit synchronizer in the xe1202a is not used, the connection rfif 1 ? clkd is not required. if the st art sequence detection is not used, the connection rfif2 ? pattern is not required.
? semtech 2006 www.semt ech.com 14-21 xe8806a/xe8807a rfif0 rfif1 rfif2 rfif3 datain dataout clkd xe1202a [clock] data xe8000 mode(0) mode(1) data sck si so rf interface parallel port hardware or software spi ss sck mosi regrfifcmd2 regrfifcmd3 regrfiftx regrfiftxsta regrfifrx regrfifrxsta regrfifrxspat re g rfifcmd1 miso [match] pattern mode(2) en dataout adparam1 adparam2 pattern1 pattern2 pattern3 pattern4 fsparam3 rtparam1 rtparam1 fsparam1 fsparam2 clkout xin figure 14-9 : configuration of the connections between the microcontroller and xe1202a this documentation shows how to set-up the data tr ansmission between the microc ontroller and the xe1202a. for detailed information on the xe1202a functi onality, external components, serial interface protocol and register set- up, please refer to the xe1202a datasheet. 14.12.2.2 microcontroller clock source derived from xe1202a crystal oscillator the xe1202a has a programmable output clock derived from the 39mhz crystal oscillator. this clock can be routed to the external clock input of the microcontroller (see figure 14-9 and t he clock block documentation). in this case, a precise clock derived from the xe1202a can be used to run the microcontroller in stead of the internal rc oscillator. the advantage is that the crystal oscillator is much more precise than the internal rc but the overall power consumption of the system will be somewhat larger. to enable the external clock output of the xe1202a, set the bit rtparam_clkout=1 and use the bits adparam_clkfreq[1:0] to select the frequency bet ween 9.75mhz and 1.22mhz (see xe1202a datasheet for details). to select the external clock in the microcontroller, set the bit enextclk = 1 in the register regsysclk . be aware that the external clock is divided by 2 at the input (see the clock block documentation for more details).
? semtech 2006 www.semt ech.com 14-22 xe8806a/xe8807a the first example below (chapter 14.12.2. 3) uses the xe1202a clock. in the ot her examples, the internal rc clock is used. 14.12.2.3 reception mode using nrz coding and the xe1202a bit and message synchronizer this rf link uses a wide band transmission in the 915mhz frequency band. the protocol of the messages received is nrz mark. the start sequence of the message is a 4 byte pattern (10101010 10101010 10101010 11010100). the received messages have a data rate of 76.8 kbit/s with a frequency deviation of 100 khz. the following paragraphs will show how to set-up the xe1202a, how to set-up the rf interface and how to handle the received data. the microcontroller der ives its clock from the xe1202a. 14.12.2.3.1 xe1202a set-up to set the xe1202a in reception mode, set the pins mode(2:0) = 100. to select the 915mhz band, the bits fsparam_band = 11. the bandwidth of the baseband filter is set to 200 khz by writing rtparam_bw = 11. the bit rate is set to 76.8 kbit/s by writing fsparam_br = 100. the bit synchronizer is enabled (rtparam_bits = 1). the pattern recognition is enabled (adparam_pattern =1) and the length of the pattern is set to 32 bit (adparam_psize = 11). the pattern is written to the 4 pattern r egisters. the output clock is enabled (rtparam_clkout = 1) and its frequency is set to 2.44 mhz (adparam_clkfreq = 01). register register address 7 6 5 4 3 2 1 0 rtparam1 00000 0 1 0 0 1 1 0 0 rtparam2 00001 0 1 0 0 0 0 0 1 fsparam1 00010 1 1 1 0 0 1 0 0 fsparam2 00011 0 0 0 0 0 0 0 0 fsparam3 00100 0 0 0 0 0 0 0 0 dataout 00101 0 0 0 0 0 0 0 0 adparam1 00110 1 1 1 0 0 0 1 0 adparam2 00111 0 0 0 0 0 0 0 0 pattern1 01000 1 0 1 0 1 0 1 0 pattern2 01001 1 0 1 0 1 0 1 0 pattern3 01010 1 0 1 0 1 0 1 0 pattern4 01011 1 1 0 1 0 1 0 0 table 14-27. xe1202 register set-up (see xe1202 datasheet for bit explanation) 14.12.2.3.2 rf interface set-up we then set-up the rf interface of the microcontroller circuit as a receiver ( rfifenrx = 1 and rfifentx = 0). the external clock frequency generated by the xe1202a is 2.44 mhz. the external clock source has to be selected by writing selextclock = 1 in regsysclock . the frequency used in the microc ontroller is half of this (see clock block documentation): 1.22 mhz. to select the correct baud rate of 76.8 kbit/s according to the equation in chapter 14.10, fine*coarse =1.22e06/(16*76.8e3)=0.99. we c an approximate this at 1 (see specification in table 14-19). this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 0000. the external bit synchronization clock is switched off by setting the bit rfifrxclock = 0. the decoder is enabled and set to nrz mark decoding by setting rfifencod = 1 and rfifpcm = 001. the external start pattern detection is enabled by setting rfifenstart = 10. the start sequence detection interrupt is enabled by setting rfifrxirqen = 001. the set-up of the interface is summarized in the table 14-28.
? semtech 2006 www.semt ech.com 14-23 xe8806a/xe8807a register contents regrfifcmd1 00000000 regrfifcmd2 10100001 regrfifcmd3 00100010 table 14-28. rf interface set-up 14.12.2.3.3 data reception in order to handle the received data by interrupt, enable the rf interface reception interrupt in the interrupt handler of the circuit. data received before the first start pattern detection after t he enabling of the interface are not relevant since we are not yet synchronized to the messages. since the star t detection interrupt has been enabled, nothing has to be done until the interrupt occurs. when the first interrupt occurs, we are synchronized to t he messages. in order to read data in an efficient way, the interrupt source is modified and set to ?rx fifo full? by writing 100 to rfifrxirqen . once this is done, we can wait for the next interrupt to download the received message. at each new interrupt, we can now read 4 bytes of the received message by reading the register regrfifrx 4 consecutive times. the interrupt s hould be served before the next byte is received since otherwise data may be lost by lack of space in the fifo (overrun error which sets the flag rfifrxfifooverrun ) or because the start sequence of the next message is detected which resets the reception fifo. when the complete message is received, the st art sequence detection interrupt may be enabled again ( rfifrxirqen = 001) and the sequence starts all over again. 14.12.2.4 reception mode using manchester coding this rf link uses a narrow band transmission in the 869mhz frequency band. the protocol of the messages received is manchester level. the start sequence of the me ssage is a protocol violation. the received messages have a data rate of 2.4 kbit/s (or 4.8kbaud/s in manc hester coding) with a frequency deviation of 5khz. the following paragraphs will show how to set-up the xe1202a, how to set-up the rf interface and how to handle the received data. 14.12.2.4.1 xe1202a set-up to set the xe1202a in reception mode, set the pins mode(2:0) = 100. to select the 869mhz band, the bits fsparam_band = 10. t he bandwidth of the baseband filter is set to 10khz by writing rtparam_bw = 00. the baud rate is set to 4.8 kb/s by writing fsparam_br = 000. the bit synchronizer is enabled (rtparam_bits = 1). the pattern recogni tion is disabled (adparam_pattern =0). register register address 7 6 5 4 3 2 1 0 rtparam1 00000 0 1 0 0 0 0 0 0 rtparam2 00001 0 1 0 0 0 0 0 0 fsparam1 00010 1 0 0 0 0 0 0 0 fsparam2 00011 0 0 0 0 0 0 0 0 fsparam3 00100 0 0 0 0 0 0 0 0 dataout 00101 0 0 0 0 0 0 0 0 adparam1 00110 0 0 0 0 0 0 0 0 adparam2 00111 0 0 0 0 0 0 0 0
? semtech 2006 www.semt ech.com 14-24 xe8806a/xe8807a pattern1 01000 0 0 0 0 0 0 0 0 pattern2 01001 0 0 0 0 0 0 0 0 pattern3 01010 0 0 0 0 0 0 0 0 pattern4 01011 0 0 0 0 0 0 0 0 table 14-29. xe1202a register set-up (see xe1202a datasheet for bit explanation) 14.12.2.4.2 rf interface set-up we then set-up the rf interface of the microcontroller circuit as a receiver ( rfifenrx = 1 and rfifentx = 0). assume that the rc clock frequency used in the microcontroller is 1.0 mhz. to select the correct baud rate of 4.8 kbit/s according to the equation in chapter 14.10 (attention: the baud rate is twice the bit rate in the manchester code), fine*coarse =1.0e06/(16*4.8e3)=13.0. this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 1100. the external bit synchronization clock is switched off by clearing the bit rfifrxclock = 0. the decoder is enabled and set to manchester level decoding by setting rfifencod = 1 and rfifpcm = 011. the start detection by protocol violation is enabled by setting rfifenstart = 01. the start sequence detection interrupt is enabled by setting rfifrxirqen = 001. the set-up of the interface is summarized in the table 14-30. register contents regrfifcmd1 00000010 regrfifcmd2 10100100 regrfifcmd3 00100010 table 14-30. rf interface set-up 14.12.2.4.3 data reception in order to handle the received data by interrupt, enable the rf interface reception interrupt in the interrupt handler of the circuit. data received before the first start pattern detection after t he enabling of the interface are not relevant since we are not yet synchronized to the messages. sine the start detection interrupt has been enabled, nothing has to be done until the interrupt occurs. when the first interrupt occurs, we are synchronized to t he messages. in order to read data in an efficient way, the interrupt source is modified and set to ?rx fifo full? by writing 100 to rfifrxirqen . once this is done, we can wait for the next interrupt to download the received message. at each new interrupt, we can now read 4 bytes of the received message by reading the register regrfifrx 4 consecutive times. the interrupt s hould be served before the next byte is received since otherwise data may be lost by lack of space in the fifo (overrun error which sets the flag rfifrxfifooverrun ) or because the start sequence of the next message is detected which resets the reception fifo. when the complete message is received, the st art sequence detection interrupt may be enabled again ( rfifrxirqen = 001) and the sequence starts all over again.
? semtech 2006 www.semt ech.com 14-25 xe8806a/xe8807a 14.12.2.5 transmission mode using nrz coding this rf link uses a wide band transmission in the 915mhz frequency band. the protocol of the messages to be sent is nrz level. the start sequence of the message is a 4 byte pattern (10101010 10101010 10101010 11010100). the messages have a data rate of 76.8 kbit/s wi th a frequency deviation of 100 khz. the output power is 0 dbm. the following paragraphs will show how to se t-up the xe1202a, how to set-up the rf interface and how to handle the received data. 14.12.2.5.1 xe1202a set-up to set the xe1202a in transmission mode, set the pins mode(2:0) = 111. to select the 915mhz band, the bits fsparam_band = 11. the frequency deviation is set to 100khz by writing rtparam_dev = 11. the baud rate is set to 76.8 kbit/s by writing fsparam_br = 100. the output power is set to 0 dbm by writing rtparam_tpow = 00. the se tup of the xe1202a is shown in table 14-31. register register address 7 6 5 4 3 2 1 0 rtparam1 00000 0 0 0 0 0 0 0 0 rtparam2 00001 0 1 0 0 0 0 0 0 fsparam1 00010 1 1 1 0 0 1 0 0 fsparam2 00011 0 0 0 0 0 0 0 0 fsparam3 00100 0 0 0 0 0 0 0 0 dataout 00101 0 0 0 0 0 0 0 0 adparam1 00110 0 0 0 0 0 0 0 0 adparam2 00111 0 0 0 0 0 0 0 0 pattern1 01000 0 0 0 0 0 0 0 0 pattern2 01001 0 0 0 0 0 0 0 0 pattern3 01010 0 0 0 0 0 0 0 0 pattern4 01011 0 0 0 0 0 0 0 0 table 14-31. xe1202a register set-up (see xe1202a datasheet for bit explanation) 14.12.2.5.2 rf interface set-up we then set-up the rf interface of the microcontroller circuit as a transmitter ( rfifenrx = 0 and rfifentx = 1). assume that the rc clock frequency used in the microcontroller is 1.2 mhz. to select the correct baud rate of 76.8 kbit/s according to the equation in chapter 14.10, fine*coarse =1.2e06/(16*76.8e3)=0.98. we can approximate this at 1 (see specification in tabl e 14-19). this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 0000. the external bit synchronization clock is switched off by clearing the bit rfiftxclock = 0. the encoder is enabled and set to nrz level encoding by setting rfifencod = 1 and rfifpcm = 000. the set-up of the interface is summarized in the table 14-32. register contents regrfifcmd1 00000000 regrfifcmd2 00100010 regrfifcmd3 00000001 table 14-32. rf interface set-up
? semtech 2006 www.semt ech.com 14-26 xe8806a/xe8807a 14.12.2.5.3 data transmission to handle the transmission data by interrupt, enable the rf in terface transmission interrupt in the interrupt handler of the circuit. we need to send the start sequence (preamble) first. the start sequence is defined as 10101010 10101010 10101010 11010100. since the nrz level encoder is enabled, as ?10101010?, ?10101010?, ?10101010? and ?11010100? should be written to the register regrfiftx . the fifo is now full, and we can wait for the interrupt which will indicate that the fifo is empty. at occurrence of the interrupt, 4 bytes of the message can be written to the fifo until all message bytes are sent. 14.12.2.6 transmission mode using manchester code this rf link uses a transmission in the 433mhz frequency band. the protocol of the messages to be sent is manchester space. the start sequence of the message is a code violation. the messages have a data rate of 19.2 kbit/s with a frequency deviation of 40 khz. the output power is 15 dbm. the following paragraphs will show how to set-up the xe1202a, how to set-up the rf interface and how to handle the received data. 14.12.2.6.1 xe1202a set-up to set the xe1202a in transmission mode, set the pins mode(2:0) = 111. to select the 433 mhz band, the bits fsparam_band = 01. the frequency deviation is set to 40 khz by writing rtparam_dev = 10. the baud rate is set to 38.4 kb/s by writing fsparam_br = 011. the output power is set to 15 dbm by writing rtparam_tpow = 11. the set up of the xe1202a is shown in table 14-33. register register address 7 6 5 4 3 2 1 0 rtparam1 00000 0 0 0 0 0 0 1 1 rtparam2 00001 0 1 0 0 0 0 0 0 fsparam1 00010 0 1 0 1 1 0 1 1 fsparam2 00011 0 0 0 0 0 0 0 0 fsparam3 00100 0 0 0 0 0 0 0 0 dataout 00101 0 0 0 0 0 0 0 0 adparam1 00110 0 0 0 0 0 0 0 0 adparam2 00111 0 0 0 0 0 0 0 0 pattern1 01000 0 0 0 0 0 0 0 0 pattern2 01001 0 0 0 0 0 0 0 0 pattern3 01010 0 0 0 0 0 0 0 0 pattern4 01011 0 0 0 0 0 0 0 0 table 14-33. xe1202a register set-up (see xe1202a datasheet for bit explanation) 14.12.2.6.2 rf interface set-up we then set-up the rf interface of the microcontroller circuit as a transmitter ( rfifenrx = 0 and rfifentx = 1). assume that the rc clock frequency used in the microcontroller is 1.2 mhz. to select the correct baud rate of 19.2 kbit/s according to the equation in chapter 14.10 (attention: the baud rate is twice the bit rate in the manchester code), fine*coarse =1.2e06/(16*38.4e3)=1.95. we can approximate this at 2. this can be done by setting rfifbrcoarse = 00 and rfifbrfine = 0001. the external bit synchronization clock is switched off by clearing the bit rfiftxclock = 0. the encoder is enabled and set to manchester space encoding by setting rfifencod = 1 and rfifpcm = 010. the set-up of the interface is summarized in table 14-34.
? semtech 2006 www.semt ech.com 14-27 xe8806a/xe8807a register contents regrfifcmd1 00000001 regrfifcmd2 00100010 regrfifcmd3 00000001 table 14-34. rf interface set-up 14.12.2.6.3 data transmission to handle the transmission data by interrupt, enable the rf in terface transmission interrupt in the interrupt handler of the circuit. we need to send the start sequence first. t he start sequence is defined as a protoc ol violation. to send a protocol violation, the encoder has to be disabled by clearing rfifencod = 0. we then can write for instance ?00000000? to rfiftx . at occurrence of the interrupt, the start sequence was transfe rred to the shift register and the fifo is empty. the encoder is to be enabled by setting rfifencod = 1. we do not need to wait until the start sequence transmission is completed, since the modification of the bit rfifencod is taken into account only at the transfer of the next byte from the fifo to the transmission shift register. t he first 4 bytes of the message can then be written to rfiftx . at each occurrence of the interrupt, 4 bytes of the mess age can be written to the fifo until the end of the message is reached. the whole operation star ts over again for the next message.
? semtech 2006 www.semtech.com 15-1 xe8806a/xe8807a 15. universal asynchronous receiver/transmitter (uart) 15.1 features .................................................................................................................. ......................... 15-2 15.2 overview .................................................................................................................. ........................ 15-2 15.3 registers map ............................................................................................................. ..................... 15-2 15.4 interrupts map ............................................................................................................ ...................... 15-3 15.5 uart baud ra te selection.................................................................................................. .............. 15-3 15.6 uart on the rc oscillator or external cl ock sour ce ....................................................................... 1 5-3 15.7 uart on the cr ystal oscillator............................................................................................ .............. 15-4 15.8 function description...................................................................................................... ................... 15-5 15.8.1 configur ation bits ...................................................................................................... ....................... 15-5 15.8.2 transmission............................................................................................................ ........................ 15-5 15.8.3 reception ............................................................................................................... .......................... 15-6 15.8.4 interrupt or polling .................................................................................................... ........................ 15-7 15.9 softwar e hints ............................................................................................................ ...................... 15-7
? semtech 2006 www.semtech.com 15-2 xe8806a/xe8807a 15.1 features ? full duplex operation with buffered receiver and transmitter. ? internal baudrate generator with 10 programmable baudrates (300 - 153600). ? 7 or 8 bits word length. ? even, odd, or no-parity bit generation and detection ? 1 stop bit ? error receive detection: start, parity, frame and overrun ? receiver echo mode ? 2 interrupts (receive full and transmit empty) ? enable receive and/or transmit ? invert pad rx and/or tx 15.2 overview the uart pins are pb[7], which is used as rx - receive and pb[6] as tx - transmit. 15.3 registers map register name reguartctrl reguartcmd reguarttx reguarttxsta reguartrx reguartrxsta table 15-1: uart register default addresses pos. reguartcmd rw reset description 7 selxtal r/w 0 nresetglobal select i nput clock: 0 = rc/external, 1 = xtal 6 - r 0 unused 5-3 uartrcsel(2:0) r/w 000 nreset global rc prescaler selection 2 uartpm r/w 0 nresetglobal select parity mode: 1 = odd, 0 = even 1 uartpe r/w 0 nresetglobal enable parity: 1 = with parity, 0 = no parity 0 uartwl r/w 1 nresetglobal select word length: 1 = 8 bits, 0 = 7 bits table 15-2: reguartcmd pos. reguartctrl rw reset description 7 uartecho r/w 0 nresetglobal enable echo mode: 1 = echo rx->tx, 0 = no echo 6 uartenrx r/w 0 nresetglob al enable uart reception 5 uartentx r/w 0 nresetglobal enable uart transmission 4 uartxrx r/w 0 nresetglobal invert pad rx 3 uartxtx r/w 0 nresetglobal invert pad tx 2-0 uartbr(2:0) r/w 101 nresetglobal select baud rate table 15-3: reguartctrl
? semtech 2006 www.semtech.com 15-3 xe8806a/xe8807a pos. reguarttx rw reset description 7-0 uarttx r/w 00000000 nresetglobal data to be send table 15-4: reguarttx pos. reguarttxsta rw reset description 7-2 - r 000000 unused 1 uarttxbusy r 0 nresetglobal uart busy transmitting 0 uarttxfull r 0 nresetglobal reguarttx full set by writing to reguarttx cleared when transferring reguarttx into internal shift register table 15-5: reguarttxsta pos. reguartrx rw reset description 7-0 uartrx r 00000000 nresetglobal received data table 15-6: reguartrx pos. reguartrxsta rw reset description 7-6 - r 00 unused 5 uartrxserr r 0 nresetglobal start error 4 uartrxperr r 0 nresetglobal parity error 3 uartrxferr r 0 nresetglobal frame error 2 uartrxoerr r/c 0 nres etglobal overrun error cleared by writing reguartrxsta 1 uartrxbusy r 0 nresetglob al uart busy receiving 0 uartrxfull r 0 nresetglobal reguartrx full cleared by reading reguartrx table 15-7: reguartrxsta 15.4 interrupts map interrupt source default mapping in the interrupt manager irq_uart_tx irqhig(1) irq_uart_rx irqhig(0) table 15-8: interrupts map 15.5 uart baud rate selection in order to have correct baud rates, the uart interface ha s to be fed with a stable and trimmed clock source. the clock source can be an external clock source, the rc osc illator or the crystal oscillator. the precision of the baud rate will depend on the precision of the selected clock source. 15.6 uart on the rc oscillator or external clock source to select the external clock or rc oscillator for the uart, the bit selxtal in reguartcmd has to be 0. the choice between the rc oscillator and the external clock source is made with the bit enextclock in regsysclock .
? semtech 2006 www.semtech.com 15-4 xe8806a/xe8807a in order to obtain a co rrect baud rate, the rc oscillator or external clock frequency have to be set to one of the frequencies given in the table below. the precision of t he obtained baud rate is directly proportional to the frequency deviation of the used clock source wi th respect to the values in the table below. frequency selection for correct uart baud rates rc oscillator (hz) external clock (hz) 2?457?600 4?915?200 1?228?800 2?457?600 614?400 1?228?800 307?200 614?400 153?600 307?200 76?800 153?600 table 15-9a for each of these frequencies, the ba ud rate can be selected with the bits uartbr(2:0) in reguartctrl and uartrcsel(2:0) in reguartcmd as shown in table 15-9. rc frequency (hz) 2457600 1228800 614400 307200 153600 76800 external clock freq. (hz) 4915200 2457600 1228800 614400 307200 153600 uartrcsel uartbr 111 153600 76800 38400 19200 9600 4800 110 76800 38400 19200 9600 4800 2400 101 38400 19200 9600 4800 2400 1200 100 19200 9600 4800 2400 1200 600 011 9600 4800 2400 1200 600 300 010 4800 2400 1200 600 300 - 001 2400 1200 600 300 - - 000 000 1200 600 300 - - - 001 600 300 - - - - 010 000 300 - - - - - table 15-9: uart baud rate with rc clock or external clock note 1 : although not documented here, the coding of the baud rate used in the circuits xe8801, xe8803 and xe8805 can also be used. note 2 : the precision of the baud rate is directly proportional to the frequency deviation of the used clock from the ideal frequency given in the table. in order to increase the precision and stability of the rc oscillator, the dfll (digital frequency locked lo op) can be used with the crysta l oscillator as a reference. 15.7 uart on the crystal oscillator in order to use the crysta l oscillator as the clock source for the uart, the bit selxtal in reguartcmd has to be set. the crystal oscillator has to be enabled by setting the enablextal bit in regsysclock . the baud rate selection is done using the uartbr bits as shown in table 15-10. xtal freq. (hz) 32768 uartbr 011 2400 010 1200 001 600 000 300 table 15-10: uart baud rate with xtal clock
? semtech 2006 www.semtech.com 15-5 xe8806a/xe8807a due to the odd ratio between the crystal oscillator fr equency and the baud rate, the generated baud rate has a systematic error of ?2.48%. 15.8 function description 15.8.1 configuration bits the configuration bits of the uart seri al interface can be found in the registers reguartcmd and reguartctrl . the bit selxtal is used to select the clock source (see chapter 15.5). the bits uartselrc and uartbr select the baud rate (see chapter 15.5). the bits uartenrx and uartentx are used to enable or disable the reception and transmission. the word length (7 or 8 data bits) can be chosen with uartwl . a parity bit is added during transmission or checked during reception if uartpe is set. the parity mode (odd or even) can be chosen with uartpm . setting the bits uartxrx and uartxtx inverts the rx respectively tx signals. the bit uartecho is used to send the received data automatically back. the transmission function becomes then: tx = rx xor uartxrx xor uartxtx . 15.8.2 transmission in order to send data, the transmitter has to be enabled by setting the bit uartentx . data to be sent have to be written to the register reguarttx . the bit uarttxfull in reguarttxsta then goes to 1, indicating to the transmitter that a new word is available. as soon as the transmitte r has finished sending the previous word, it then loads the contents of the register reguarttx to an internal shift register and clears the uarttxfull bit. an interrupt is generated on irq_uart_tx at the falling edge of the uarttxfull bit. the bit uarttxbusy in reguarttxsta shows that the transmitter is busy transmitting a word. a timing diagram is shown in figure 15-1. data is sent lsb first. new data should be written to the register reguarttx only while uarttxbusy is 0, otherwise data will be lost.
? semtech 2006 www.semtech.com 15-6 xe8806a/xe8807a asynchronous transmission w rite to re g uarttx re g uarttx word 1 reguarttx_shift word 1 shift clock tx start b0 b1 b6/7 parity stop uarttxbus y uarttxfull irq_uart_tx asynchronous transmission (back to back) word 1 word 2 w rite to re g uarttx re g uarttx word 1 word 2 reguarttx_shift word 1 word 2 shift clock tx start b0 b6/7 stop start uarttxbus y uarttxfull irq_uart_tx figure 15-1. uart tran smission timing diagram. 15.8.3 reception on detection of the start bit, the uartrxbusy bit is set. on detection of the stop bit, the received data are transferred from the internal shift register to the register reguartrx . at the same time, the uartrxfull bit is set and an interrupt is generated on irq_uart_rx. this indicates that new data is available in reguartrx . the timing diagram is shown in figure 15-2. the uartrxfull bit is cleared when reguartrx is read. if the register was not read before the receiver transfers a new word to it, the bit uartrxoerr (overflow error) is set and the previous contents of the register are lost. uartrxoerr is cleared by writing any data to reguartrxsta . the bit uartrxserr is set if a start error has been detected. the bit is updated at data transfer to reguartrx . the bit uartrxperr is set if a parity error has been detected, i.e. t he received parity bit is not equal to the calculated parity of the received data. the bit is updated at data transfer to reguartrx . the bit uartrxferr in reguartrxsta shows that a frame error has been detected. no stop bit has been detected.
? semtech 2006 www.semtech.com 15-7 xe8806a/xe8807a asynchronous reception read of reguartrx (software) reguartrx_shift word 1 reguartrx word 1 shift clock rx start b0 b6/7 parity stop uartrxbusy uartrxfull irq_uart_rx figure 15-2. uart reception timing diagram. 15.8.4 interrupt or polling the transmission and reception software can be driv en by interruption or by polling the status bits. interrupt driven reception: each time an irq_uart_rx in terrupt is generated, a new word is available in reguartrx . the register has to be read before a new word is received. interrupt driven transmission: each time the contents of reguarttx is transferred to the transmission shift register, an irq_uart_tx interrupt is generated. a new word can then be written to reguarttx . reception driven by polling: the uartrxfull bit is to be read and checked. when it is 1, the reguartrx register contains new data and has to be read before a new word is received. transmission driven by polling: the uarttxfull bit is to read and checked. when it is 0, the reguarttx register is empty and a new word can be written to it. 15.9 software hints example of program for a transmission with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. wait untill the uarttxfull bit in reguarttxsta register equals 0. 4. jump to 2 to writing the next byte if the message is not finished. 5. end of transmission. example of program for a transmission with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. after an interrupt and if the message is not finished, jump to 2 4. end of transmission.
? semtech 2006 www.semtech.com 15-8 xe8806a/xe8807a example of program for a reception with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. wait until the uartrxfull bit in the reguartrxsta register equals 1. 3. read the reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception. example of program for a reception with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. when there is an interrupt, jump to 3 3. read reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception.
? semtech 2006 www.semtech.com 16-1 xe8806a/xe8807a 16. universal synchronous receiver/transmitter (usrt) 16.1 features .................................................................................................................. ..............................16-2 16.2 overview .................................................................................................................. .............................16-2 16.3 register map.............................................................................................................. ...........................16-2 16.4 interrupts map............................................................................................................ ...........................16-4 16.5 conditional e dge detection 1 .............................................................................................. ..................16-4 16.6 conditional e dge detection 2 .............................................................................................. ..................16-4 16.7 interrupts or polling ..................................................................................................... ..........................16-5 16.8 function description...................................................................................................... ........................16-5
? semtech 2006 www.semtech.com 16-2 xe8806a/xe8807a 16.1 features the usrt implements a hardware support fo r software implemented serial protocols: ? control of two external lines s0 and s1 (read/write). ? conditional edge detection generates interrupts. ? s0 rising edge detection. ? s1 value is stored on s0 rising edge. ? s0 signal can be forced to 0 after a falling edge on s0 for clock stretching in the low state. ? s0 signal can be stretched in the low state after a falling edge on s0 and after a s1 conditional detection. 16.2 overview the usrt block supports software universal synchr onous receiver and transmitter mode interfaces. external lines s0 and s1 respectively correspond to cloc k line and data line. s0 is mapped to pb[4] and s1 to pb[5] when the usrt block is enabled. it is independent of regpbdir (port b can be input or output). when usrt is enabled, the configurations in port b for pb[4 ] and pb[5] are overwritten by the usrt configuration. internal pull-ups can be used by setting the pbpullup[5:4] bits. conditional edge detections are provided. regusrts1 can be used to read the s1 data line from pb[5] in receive mode or to drive the output s1 line pb[5] by writing it when in transmit mode. it is advised to read s1 data when in receive mode from the regusrtbuffers1 register, which is the s1 value sampled on a rising edge of s0. 16.3 register map register name regusrts1 regusrts0 regusrtctrl regusrtcond1 regusrtcond2 regusrtbuffers1 regusrtedges0 table 16-1: usrt registers block configurat ion registers: pos. regusrts1 rw reset function 7-1 ?0000000? r - unused 0 usrts1 r/w 1 nresetglobal write: data s1 written to pad pb[5]), read: value on pb[5] (not usrts1 value). table 16-2: regusrts1
? semtech 2006 www.semtech.com 16-3 xe8806a/xe8807a pos. regusrts0 rw reset function 7-1 ?0000000? r - unused 0 usrts0 r/w 1 nresetglobal write: clock s0 written to pad pb[4], read: value on pb[4] (not usrts0 value). table 16-3: regusrts0 the values that are read in the registers regusrts1 and regusrts0 are not necessarily the same as the values that were written in the register. the read value is read back on the circuit pins not in the registers themselves. since the outputs are open drain, an external circuit on the circuit pins may forc e a value different from the register value. pos. regusrtctrl rw reset function 7-4 ?0000? r - unused 3 usrtwaits0 r 0 nresetglobal clo ck stretching flag (0=no stretching), cleared by writing regusrtbuffers1 2 usrtenwaitcond1 r/w 0 nresetglobal enable stretching on usrtcond1 detection (0=disable) 1 usrtenwaits0 r/w 0 nresetglobal e nable stretching operation (0=disable) 0 usrtenable r/w 0 nresetglobal enable usrt operation (0=disable) table 16-4: regusrtctrl pos. regusrtcond1 rw reset function 7-1 ?0000000? r - unused 0 usrtcond1 r/c 0 nresetglobal state of condition 1 detection (1 =detected), cleared when written. table 16-5: regusrtcond1 pos. regusrtcond2 rw reset function 7-1 ?0000000? r - unused 0 usrtcond2 r/c 0 nresetglobal state of condition 2 detection (1 =detected), cleared when written. table 16-6: regusrtcond2 pos. regusrtbuffers1 rw reset function 7-1 ?0000000? r - unused 0 usrtbuffers1 r 0 nresetglobal val ue on s1 at last s0 rising edge. table 16-7: regusrtbuffers1 pos. regusrtedges0 rw reset function 7-1 ?0000000? r - unused 0 usrtedges0 r 0 nresetglobal st ate of rising edge detection on s0 (1=detected). cleared by reading regusrtbuffers1 table 16-8: regusrtedges0
? semtech 2006 www.semtech.com 16-4 xe8806a/xe8807a 16.4 interrupts map interrupt source default mapping in the interrupt manager irq_cond2 regirqmid(7) irq_cond1 regirqmid(6) table 16-9: interrupts map 16.5 conditional edge detection 1 s1 s0 figure 16-1: condition 1 condition 1 is satisfied when s0=1 at the falling edge of s1. the bit usrtcond1 in regusrtcond1 is set when the condition 1 is detected and the usrt interface is enabled ( usrtenable =1). condition 1 is asserted for both modes (receiver and transmitter). the usrtcond1 bit is read only and is cleared by all reset conditions and by writing any data to its address. condition 1 occurrence also generates an interrupt on irq_cond1. 16.6 conditional edge detection 2 s1 s0 figure 16-2: condition 2 condition 2 is satisfied when s0=1 at the rising edge of s1. the bit usrtcond2 in regusrtcond2 is set when the condition 2 is detected and the usrt interface is enabled. condition 2 is asserted for both modes (receiver and transmitter). the usrtcond2 bit is read only and is cleared by all reset conditions and by writing any data to its address. condition 2 occurrence also generates an interrupt on irq_cond2.
? semtech 2006 www.semtech.com 16-5 xe8806a/xe8807a 16.7 interrupts or polling in receive mode, there are two possibilities to detect cond ition 1 or 2: the detection of the condition can generate an interrupt or the registers can be polled (reading and checking the regusrtcond1 and regusrtcond2 registers for the status of usrt communication). 16.8 function description the bit usrtenable in regusrtctrl is used to enable the usrt interfac e and controls the pb[4] and pb[5] pins. this bit puts these two port b lines in the open drain configuration requested to use the usrt interface. if no external pull-ups are added on pb[4] and pb[5], the user can activate internal pull-ups by setting pbpullup[4] and pbpullup[5] in regpbpullup . the bits usrtenwaits0 , usrtenwaitcond1 , usrtwaits0 in regusrtctrl are used for transmitter/receiver control of usrt interface. figure 16-3 shows the unconditi onal clock stretching function which is enabled by setting usrtenwaits0. s0 us r tw ai ts 0 write reg usrtbuffers1 figure 16-3: s0 stretching (usrtenwaits0=1) when usrtenwaits0 is 1, the s0 line will be maintained at 0 after its falling edge (clock stretching). usrtwaits0 is then set to 1, indicating that the s0 line is forc ed low. one can release s0 by writing to the regusrtbuffers1 register. the same can be done in combination with condition 1 detection by setting the usrtenwaitcond1 bit. figure 16-4 shows the conditional clock stretching function, which is enabled by setting usrtenwaitcond1 .
? semtech 2006 www.semtech.com 16-6 xe8806a/xe8807a s0 us r tw ai ts 0 write reg usrtbuffers1 s1 figure 16-4: conditional stre tching (usrtenwaitcond1=1) when usrtenwaitcond1 is 1, the s0 signal will be stretched in its low state after its falling edge if the condition 1 has been detected before ( usrtcond1 =1). usrtwaits0 is then set to 1, indicating that the s0 line is forced low. one can release s0 by writing to the regusrtbuffers1 register. figure 16-5 shows the sampling function implemented by the usrtbuffers1 bit. the bit usrtbuffers1 in regusrtbuffers1 is the value of s1 sampled on pb[4] at the last rising edge of s0. the bit usrtedges0 in regusrtedges0 is set to one on the same s0 rising edge and is cleared by a read operation of the regusrtbuffers1 register. the bit therefor indicates that a new value is present in the regusrtbuffers1 which was not yet read. s0 usrtbuffers1 read reg usrtbuffers1 s1 us r t edg e s 0 figure 16-5: s1 sampling
? semtech 2006 www.semtech.com 17-1 xe8806a/xe8807a 17. counters/pwm 17. counte rs/pwm ............................................................................................................... .................. 17-1 17.1 features .................................................................................................................. ........................... 17-2 17.2 overview .................................................................................................................. .......................... 17-2 17.3 register map.............................................................................................................. ........................ 17-2 17.4 interrupts an d events map ................................................................................................. ................ 17-4 17.5 block schematic ........................................................................................................... ...................... 17-4 17.6 general counter r egisters operation ....................................................................................... ........... 17-5 17.7 clock selection........................................................................................................... ........................ 17-5 17.8 counter mode selection .................................................................................................... ................. 17-6 17.9 counter / timer mode ...................................................................................................... .................. 17-7 17.10 pwm mode ................................................................................................................. ....................... 17-8 17.11 captur e function......................................................................................................... ........................ 17-9 17.12 specif ications ........................................................................................................... ........................ 17-10
? semtech 2006 www.semtech.com 17-2 xe8806a/xe8807a 17.1 features - 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules - each with 4 possible clock sources - up/down counter modes - interrupt and event generation - capture function (internal or external source) - rising, falling or both edge of capture signal (except for xtal 32 khz, only rising edge) - pa[3:0] can be used as clock inputs (debounced or direct, frequency divided by 2 or not) - 2 x 8 bits pwm or 2 x 16 bits pwm - pwm resolution of 8, 10, 12, 14 or 16 bits - complex mode combinations are possible 17.2 overview counter a and counter b are 8-bits counters and can be combined to form a 16-bit counter. counter c and counter d exhibit the same feature. the counters can also be used to generate two pwm outputs on pb[0] and pb[1]. in pwm mode one can generate pwm functions with 8, 10, 12, 14 or 16 bits wide counters. the counters a and b can be captured by events on an in ternal or an external signal. the capture can be performed on both 8-bit counters running individually on two different clock sources or on both counters chained to form a 16-bit counter. in any case, the same capture signal is used for both counters. when the counters a and b are not chai ned, they can be used in several co nfigurations: a and b as counters, a and b as captured counters, a as pwm and b as counter, a as pwm and b as captured counter. when the counters c and d are not chained, they can be used either both as counters or counter c as pwm and counter d as counter. 17.3 register map register name regcnta regcntb regcntc regcntd regcntctrlck regcntconfig1 regcntconfig2 regcnton table 17-1. counter registers bit regcnta rw reset function 7-0 countera r 00000000 nresetglobal 8-bits counter value 7-0 countera w 00000000 nresetglobal 8-bits comparison value table 17-2. regcnta
? semtech 2006 www.semtech.com 17-3 xe8806a/xe8807a bit regcntb rw reset function 7-0 counterb r 00000000 nresetglobal 8-bits counter value 7-0 counterb w 00000000 nresetglobal 8-bits comparison value table 17-3. regcntb note: when writing to regcnta or regcntb , the processor writes the counter comparison values. when reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit regcntc rw reset function 7-0 counterc r 00000000 nresetglobal 8-bits counter value 7-0 counterc w 00000000 nresetglobal 8-bits comparison value table 17-4. regcntc bit regcntd rw reset function 7-0 counterd r 00000000 nresetglobal 8-bits counter value 7-0 counterd w 00000000 nresetglobal 8-bits comparison value table 17-5. regcntd note: when writing regcntc or regcntd , the processor writes the counter comparison values. when reading these locations, the processor read s back the actual counter value. bit regcntctrlck rw reset function 7-6 cntdcksel(1:0) rw 00 nresetglobal counter d clock selection 5-4 cntccksel(1:0) rw 00 nresetglobal counter c clock selection 3-2 cntbcksel(1:0) rw 00 nresetglobal counter b clock selection 1-0 cntacksel(1:0) rw 00 nresetglobal counter a clock selection table 17-6. regcntctrlck bit regcntconfig1 rw reset function 7 cntddownup rw 0 nresetglobal counter d up or down counting (0=down) 6 cntcdownup rw 0 nresetglobal counter c up or down counting (0=down) 5 cntbdownup rw 0 nresetglobal counter b up or down counting (0=down) 4 cntadownup rw 0 nresetglobal counter a up or down counting (0=down) 3 cascadecd rw 0 nresetglobal cascade counter c & d (1=cascade) 2 cascadeab rw 0 nresetglobal cascade counter a & b (1=cascade) 1 cntpwm1 rw 0 nresetglobal activate pwm1 on counter c or c+d (pb(1)) 0 cntpwm0 rw 0 nresetglobal activate pwm0 on counter a or a+b (pb(0)) table 17-7. regcntconfig1 bit regcntconfig2 rw reset function 7-6 capsel(1:0) rw 00 nresetglobal capture source selection 5-4 capfunc(1:0) rw 00 nresetglobal capture function 3-2 pwm1size(1:0) rw 00 nresetglobal pwm1 size selection 1-0 pwm0size(1:0) rw 00 nresetglobal pwm0 size selection table 17-8. regcntconfig2
? semtech 2006 www.semtech.com 17-4 xe8806a/xe8807a bit regcnton rw reset function 7 cntdextdiv rw 0 nresetglobal di vide pa(3) frequency by 2 (1=divide) 6 cntcextdiv rw 0 nresetglobal di vide pa(2) frequency by 2 (1=divide) 5 cntbextdiv rw 0 nresetglobal divide pa(1) frequency by 2 (1=divide) 4 cntaextdiv rw 0 nresetglobal divide pa(0) frequency by 2 (1=divide) 3 cntdenable rw 0 nresetglobal enable counter d 2 cntcenable rw 0 nresetglobal enable counter c 1 cntbenable rw 0 nresetglobal enable counter b 0 cntaenable rw 0 nresetglobal enable counter a table 17-9. regcnton 17.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager irqa regirqhigh(4) regevn(7) irqb regirqlow(5) regevn(3) irqc regirqhigh(3) regevn(6) irqd regirqlow(4) regevn(2) table 17-10. default interrupt and event mapping. 17.5 block schematic figure 17-1: counters/timers block schematic pb(0) capture ck16k ck1k pa(0) regcnta (write) counter a pa(2) regcntc (write) counter c regcntd (write) counter d regcntb (write) counter b pa(1) pa(3) ck128 c krcext/4 ckrcext ck1k ck32k pwm pb(1) regcnta (read) regcntb (read) regcntc (read) regcntd (read)
? semtech 2006 www.semtech.com 17-5 xe8806a/xe8807a 17.6 general counter registers operation counters are enabled by cntaenable , cntbenable , cntcenable , and cntdenable in regcnton . to stop the counter x, cnt x enable must be reset. to start the counter x, cnt x enable must be set. when counters are cascaded, cntaenable and cntcenable also control respectively the counters b and d. all counters have a corresponding 8-bit read/write register: regcnta , regcntb , regcntc , and regcntd . when read, these registers contain the counter value (or the ca ptured counter value). when written, they modify the counter comparison values. it is possible to read any counter at any time, even when the counter is running. the value is guaranteed to be correct when the counter is running on an internal clock source. for a correct acquisition of the counter value when running on an external clock source, us e one of the three following methods: 1) for slow operating counters (typic ally at least 8 times slower than t he cpu clock), oversample the counter content and perform a majority operation on the cons ecutive read results to select the correct actual content of the counter. 2) stop the concerned counter, pe rform the read operation and restart the counter. while stopped, the counter content is frozen and the counter does not ta ke into account the clock edges delivered on the external pin. 3) use the capture mechanism. when a value is written into the counter register while t he counter is in counter mode, both the comparison value is updated and the counter value is modified. in upcount mode, the register value is reset to zero. in downcount mode, the comparison value is loaded into the count er. due to the synchronization mechanism between the processor clock domain and the external clock source do main, this modification of the counter value can be postponed until the counter is enabled and that it receives it?s first valid clock edge. in the pwm mode or in the capture mode, the counter value is not modified by the write operation in the counter register. changing to the counter mode, does not update the counter value (no reset in upcount, no load in downcount mode). 17.7 clock selection the clock source for each counter can be individually sele cted by writing the appropriate value in the register regcntctrlck . table 17-11 gives the correspondence between the bi nary codes used for the configuration bits cntacksel(1:0) , cntbcksel(1:0), cntccksel(1:0) or cntdcksel(1:0) and the clock source selected respectively for the counters a, b, c or d. clock source for cnt x cksel(1:0) countera counterb counterc counterd 11 ck128 10 ckrcext/4 ck1k 01 ckrcext ck32k 00 pa(0) pa(1) pa(2) pa(3) table 17-11: clock sources for counters a, b, c and d the ckrcext clock is the rc oscillator or external clock. the clocks below 32khz can be derived from the rc oscillator, the external clock source or the crystal oscillator (see the document ation of the clock block). a separate external clock source can be delivered on porta for each individula counter.
? semtech 2006 www.semtech.com 17-6 xe8806a/xe8807a the external clock sources can be d ebounced or not by properly setting t he porta configuration registers. additionally, the external clock sources can be divided by two in the counter block, thus enabling higher external clock frequencies, by setting the cnt x extdiv bits in the regcnton register. switching between an internal and an external clock so urce can only be performed while the counter is stopped. the enabling or disabling of the exte rnal clock frequency division can only be performed while the counter using this clock is stopped, or when this counter is running on an internal clock source. 17.8 counter mode selection each counter can work in one of the following modes: 1) counter, downcount & upcount 2) captured counter, downcount & upcount (only counters a&b) 3) pwm, downcount & upcount 4) captured pwm, downcount and upcount the counters a and b or c and d can be cascaded or not. in cascaded mode, a and c are the lsb counters while b and d are the msb counters. table 17-12 shows the different operation modes of the co unters a and b as a function of the mode control bits. for all counter modes, the source of the down or upcount selection is given (either the bit cntadownup or the bit cntbdownup ). also, the mapping of the interrupt sources ir qa and irqb and the pwm output on pb(0) in these different modes is shown. cascadeab countpwm0 capfunc(1:0) counter a mode counter b mode irqa source irqb source pb(0) function 0 0 00 counter 8b downup: a counter 8b downup: b counter a counter b pb(0) 1 0 00 counter 16b ab downup: a counter ab - pb(0) 0 1 00 pwm 8b downup: a counter 8b downup: b - counter b pwm a 1 1 00 pwm 10 ? 16b ab downup a - - pwm ab 0 0 1x or x1 captured counter 8b downup: a captured counter 8b downup: b capture a capture b pb(0) 1 0 1x or x1 captured counter 16b ab downup: a capture ab capture ab pb(0) 0 1 1x or x1 captured pwm 8b downup: a captured counter 8b downup: b capture a capture b pwm a 1 1 1x or x1 captured 10 ? 16b pwm (captured value on 16b) downup: a capture ab capture ab pwm ab table 17-12: operating modes of the counters a and b table 17-13 shows the different operation modes of the co unters c and d as a function of the mode control bits. for all counter modes, the source of the down or upcount selection is given (either the bit cntcdownup or the bit cntddownup ). the mapping of the interrupt sources irqc and irqd and the pwm output on pb(1) in these different modes is also shown. the switching between different modes must be done while the concerned counters are stopped. while switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change.
? semtech 2006 www.semtech.com 17-7 xe8806a/xe8807a cascadecd countpwm1 counter c mode counter d mode irqc source irqd source pb(1) function 0 0 counter 8b downup: c counter 8b downup: d counter c counter d pb(1) 1 0 counter 16b cd downup: c counter cd - pb(1) 0 1 pwm 8b downup: c counter 8b downup: d - counter d pwm c 1 1 pwm 10 ? 16b cd downup: c - - pwm cd table 17-13: operating modes of the counters c and d 17.9 counter / timer mode the counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock periods applied on the counter clock input. each counter can be set individually either in upcount mode by setting cnt x downup in the register regcntconfig1 or in downcount mode by resetting this bit. counters a and b can be cascaded to behave as a 16 bit counter by setting cascadeab in the regcntconfig1 register. counters c and d can be cascaded by setting cascadecd . when cascaded, the up/down count modes of the counters b and d are defin ed respectively by the up/down count modes set for the counters a and c. when in upcount mode, the counter will start incrementing fr om zero up to the target value which has been written in the corresponding regcnt x register(s). when the counter content is equal to the target value, an interrupt is generated at the next counter clock pulse and the counter is loaded again with the zero value (figure 17-2). when in downcount mode, the counter will start decrementi ng from the initial load value which has been written in the corresponding regcnt x register(s) down to the zero value. once the counter content is equal to zero, an interrupt is generated at the next coun ter clock pulse and the counter is loaded again with the load value (figure 17-2). be careful to select the counter mode (no capture, not pwm, specify cascaded or not and up or down counting mode) before writing any target or load value to the regcnt x register(s). this ensures that the counter will start from the correct initial value. when counters are cascaded, both counter registers must be written to ensure that both cascaded counters will start from the correct initial values. the stopping and consecutive starting of a counter in counter mode without a target or load value write operation in between can generate an interrupt if this counter has been st opped at the zero value (downcount) or at it?s target value (upcount). this interrupt is additional to the in terrupt which has already been generated when the counter reached the zero or the target value.
? semtech 2006 www.semtech.com 17-8 xe8806a/xe8807a figure 17-2. up and down count interrupt generation. 17.10 pwm mode the counters can generate pwm signals (pulse widt h modulation) on the portb outputs pb(0) and pb(1). the pwm mode is selected by setting cntpwm1 and cntpwm0 in the regcntconfig1 register. see table 17-12 and table 17-13 for an exact description of how the setting of cntpwm1 and cntpwm0 affects the operating mode of the counters a, b, c and d according to the other configuration settings. when cntpwm0 is enabled, the pwma or pwmab output va lue overrides the value set in bit 0 of regpbout in the port b peripheral. when cntpwm1 is enabled, the pwmc or pwmcd output value overrides the value set in bit 1 of regpbout . the corresponding ports (0 and/or 1) of port b must be set in digital mode and as output and either open drain or not and pull up or not through a proper setting of the control registers of the port b. counters in pwm mode count down or up, according to the cnt x downup bit setting. no interrupts and events are generated by the counters that are in pwm mode. counters do count circularly: they restart at zero or at the maximal value (either 0xff when not cascaded or 0xffff when cascaded) when respectively an overflow or an underflow condition occurs in the counting. the internal pwm signals are low as long as the counter c ontents are higher than the pwm code values written in the regcnt x registers. they are high when the counter contents are smaller or equal to these pwm code values. in order to have glitch free outputs, the pwm outputs on pb(0) and pb(1) are sampled versions of these internal pwm signals, therefore delayed by one counter clock cycle. d own coun ti ng clock counter x regcntx _ r xx 321032103210 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable up coun ti ng clock counter x regcntx _ r xx0 12301230123 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable
? semtech 2006 www.semtech.com 17-9 xe8806a/xe8807a the pwm resolution is always 8 bits when the counter s used for the pwm signal generation are not cascaded. pwm0size(1:0) and pwm1size(1:0) in the regcntconfig2 register are used to set the pwm resolution for the counters a and b or c and d respectively when they ar e in cascaded mode. the different possible resolutions in cascaded mode are shown in table 17- 14. choosing a 16 bit pwm code which is higher than the maximum value that can be represented by the number of bits chosen for the resolution results in a pwm output which is always tied to 1. pwmxsize(1:0) resolution 11 16 bits 10 14 bits 01 12 bits 00 10 bits table 17-14: resolution selection in cascaded pwm mode small pwm code large pwm code t per t hlarge t llarge t hsmall t lsmall figure 17-3: pwm modulation examples the period of the pwm signal is given by the formula: ckcnt resolution f tper 2 = the duty cycle ratio dcr of the pwm signal is defined as: tper th dcr = dcr can be selected between resolution 2 100 % and 100 %. dcr in % in function of the regcntx content(s) is given by the relation: ( ) ? ? ? ? ? ? + = 100 , 2 regcntx 1 100 resolution min dcr 17.11 capture function the 16-bit capture register is provided to facilitate fre quency measurements. it provides a safe reading mechanism for the counters a and b when they ar e running. when the capture function is active, the processor does not read anymore the counters a and b directly, but instead reads sh adow registers located in the capture block. an interrupt is generated after a captur e condition has been met when the shadow register content is updated. the capture condition is user defined by selecting either inter nal capture signal sources der ived from the prescaler or from the external pa(2) or pa(3) ports. bo th counters use the same capture condition.
? semtech 2006 www.semtech.com 17-10 xe8806a/xe8807a when the capture function is active, the a and b counter s can either upcount or downcount. they do not count circularly: they restart at zero or at the maximal va lue (either 0xff when not cascaded or 0xffff when cascaded) when respectively an overflow or an underflow condition occurs in the counting. the capture function is also active on the counters when used to generate pwm signals. capfunc(1:0) in register regcntconfig2 determines if the capture function is enabled or not and selects which edges of the capture signal source are valid for the capt ure operation. the source of the capture signal can be selected by setting capsel(1:0) in the regcntconfig2 register. for all sources, rising, falling or both edge sensitivity can be selected. table 17-15 shows the captur e condition as a function of the setting of these configuration bits. capsel(1:0) selected capture signal capfunc selected condition capture condition 11 1 k 00 01 10 11 capture disabled rising edge falling edge both edges - 1 k rising edge 1 k falling edge 2 k 10 16 k 00 01 10 11 capture disabled rising edge falling edge both edges - 16 k rising edge 16 k falling edge 32 k 01 pa3 00 01 10 11 capture disabled rising edge falling edge both edges - pa3 rising edge pa3 falling edge pa3 both edges 00 pa2 00 01 10 11 capture disabled rising edge falling edge both edges - pa2 rising edge pa2 falling edge pa2 both edges table 17-15: capture condition selection capfunc(1:0) and capsel(1:0) can be modified only when the counters are stopped otherwise data may be corrupted during one counter clock cycle. due to the synchronization mechanism of the shadow regi sters and depending on the frequency ratio between the capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective capture condition occurred. when the counters a and b are not cascaded and do not operate on the same clock, the interruptions on irqa and irqb which inform that the capture condition was met, may appear at different moments. in this case, the processor should read the sh adow register associated to a counter only if the interruption related to this counter has been detected. an edge is detected on the capture signals only if the mini mal pulse widths of these signals in the low and high states are higher than a period of the counter clock source. 17.12 specifications parameter min typ max unit conditions 500 ns @ 1.2v pulse width in the low and high states for an external clock source, frequency division by 2 disabled 125 ns @ 2.4v 100 ns @ 1.2v pulse width in the low and high states for an external clock source, frequency division by 2 enabled 25 ns @ 2.4v pulse width of external capture signals 1 fckcnt s table 17-16: timing specifications for the counters
? semtech 2006 www.semtech.com 18-1 xe8806a/xe8807a 18 the voltage level detector 18.1 features .................................................................................................................. ........................... 18-2 18.2 overview .................................................................................................................. .......................... 18-2 18.3 register map.............................................................................................................. ........................ 18-2 18.4 interru pt map............................................................................................................. ......................... 18-2 18.5 vld ope ration ............................................................................................................. ....................... 18-3
? semtech 2006 www.semtech.com 18-2 xe8806a/xe8807a 18.1 features ? can be switched off, on or simu ltaneously with cpu activities ? generates an interrupt if power supply is below a pre-determined level 18.2 overview the voltage level detector monitors the state of the system battery. it returns a logical high value (an interrupt) in the status register if the supplied voltag e drops below the user defined level (vsb). 18.3 register map there are two registers in the vld, namely regvldctrl and regvldstat . table 18-2 shows the mapping of control bits and functionality of regvldctrl while table 18-3 describes that for regvldstat . register name regvldctrl regvldstat table 18-1: vld registers pos. regvldctrl rw reset function 7-4 -- r 0000 reserved 3 vldrange r w 0 nresetglobal vld detection voltage range for vldtune = ?011?: 0 : 1.3v 1 : 2.55v 2-0 vldtune[2:0] r w 000 nresetglobal vld tuning: 000 : +19 % 111 : -18 % table 18-2: regvldctrl pos. regvldstat rw reset function 7-3 -- r 00000 reserved 2 vldresult r 0 nresetglobal is 1 when battery voltage is below the detection voltage 1 vldvalid r 0 nresetglobal indicates when vldresult can be read 0 vlden r w 0 nresetglobal vld enable table 18-3: regvldstat 18.4 interrupt map interrupt source default mapping in the interrupt manager irqvld regirqmid(2) table 18-4: interrupt map
? semtech 2006 www.semtech.com 18-3 xe8806a/xe8807a 18.5 vld operation the vld is controlled by vldrange , vldtune and vlden . vldrange selects the voltage range to be detected, while vldtune is used to fine-tune this voltage level in 8 steps. vlden is used to enable (disable) the vld with a 1(0) value respectively. disabled, the block will dissipate no power. symbol description min typ max unit comments trimming values: note 1 vldrange vldtune 1.53 0 000 1.44 0 001 1.36 0 010 1.29 0 011 1.22 0 100 1.16 0 101 1.11 0 110 1.06 0 111 3.06 1 000 2.88 1 001 2.72 1 010 2.57 1 011 2.44 1 100 2.33 1 101 2.22 1 110 vth threshold voltage 2.13 v 1 111 t eom duration of measurement 2.0 2.5 ms note 2 t pw minimum pulse width detected 875 1350 us note 2 table 18-5: voltage level detector operation note 1: absolute precision of the threshold voltage is 10%. note 2: this timing is respected in case the internal rc or cr ystal oscillators are selected. refer to the clock block documentation in case the external clock is used. to start the voltage level detection, the user sets bit vlden . the measurement is started.after 2ms, the bit vldvalid is set to indicate that the measurement results are valid . from that time on, as long as the vld is enabled, a maskable interrupt request is sent if the voltage level fa lls below the threshold. one can also poll the vld and monitor the actual measurement result by reading the vldresult bit of the regvldstat . this result is only valid as long as the vldvalid bit is ?1?.
? semtech 2006 www.semtech.com 18-4 xe8806a/xe8807a figure 18-1 shows the timing of the vld. an in terrupt is generated on each rising edge of vldresult . figure 18-1: vld timing the threshold value should not be changed during the measurement. vbat vld_en vld_valid vld_result t eom pw pw vth
? semtech 2006 www.semtech.com 19-1 xe8806a/xe8807a 19. low power comparators 19. low power comparators...................................................................................................... ........... 19-1 19.1 features .................................................................................................................. ........................... 19-2 19.2 overview .................................................................................................................. .......................... 19-2 19.3 register map.............................................................................................................. ........................ 19-3 19.4 interru pt map............................................................................................................. ......................... 19-4
? semtech 2006 www.semtech.com 19-2 xe8806a/xe8807a 19.1 features the cmpd peripheral implements four low power comparators. ? quiescent current consumption of 1.5 a ? very low switching current ? per channel configurable interrupt ? hysteresis ? 1 mhz operation 19.2 overview figure 19-1 gives an overview of this block: 4 4 4 3 regcmpdctrl(7:5) regcmpdstat(7:4) regcmpdctrl(4:0) 5 4 regcmpdstat(3:0) 4x irqonrisingch (edge selection) enirqch (channel enable) comparator output pb[7:4] enable comparators (analog) cmpd interrrupt figure 19-1: structure of cmpd
? semtech 2006 www.semtech.com 19-3 xe8806a/xe8807a the cmpd peripheral is a 4-channel low power comparator. it is intended to compare analog input signals with an internally set threshold voltage. the comparator maintains low current consumption even if the input signal is very close to the threshold. the comparison result of each channel can be used to generate an interrupt and/or is available for polling. the comparator can be enabled or disabled by programming the enable bit in the regcmpdctrl register. when disabled, the block consumes no current. the peripheral has a single interrupt output which is a co mbination of the four channels. the combination can be chosen by programming the regcmpdctrl register. the enirqch[3:0] bits select the channel that can activate the interrupt. the irqonrisingch[2:0] bits indicate if the interrupt is generat ed on detection of the rising or falling edge of the channel. the comparison results of the peripheral can be read in the regcmpdstat register. the bits cmpdout[3:0] are the value of the comparisons at the moment the register is read. the cmpdstat[3:0] indicates which channel generated an interrupt since the register was last read. comparator specifications: sym description min typ max unit comments t pulse required input pulse width 500 ns vbat 1.2v idd q quiescent current 0.8 1.5 a 1 idd stat maximal static current 1.5 a 2 v th threshold voltage 0.7 1.1 v 3 ? v th / ? t threshold temperature drift -0.9 mv/ c v hyst threshold hysteresis 13 mv table 19-1: comparator specifications comments: 1. the quiescent current is defined for a static input vo ltage <0.5v or >1.3v. the specified consumption is the sum for all 4 channels. 2. the maximal static current is defined for any stat ic input voltage between vdd and vss. the specified consumption is the sum for all 4 channels. 3. defined with respect to vss. how to start the cmpd: to avoid unwanted irqs one has first to configure the ri sing / falling edge of the detection (bit irqonrisingch[2:0]) and to enable the comparator (bit enable). only after t hat may the user enable the channel interrupts with bit enirqch[3:0]. 19.3 register map there are two registers in the cmpd, namely regcmpdstat and regcmpdctrl . table 19-3 and table 19-4 show the mapping of the control bits and t he functionality of these registers. register name regcmpdstat regcmpdctrl table 19-2: cmpd registers
? semtech 2006 www.semtech.com 19-4 xe8806a/xe8807a pos. regcmpdstat rw reset function 7 cmpdstat[3] rc 0 nresetglobal 1: if the channel 3 generated an interrupt since last read of this register 6 cmpdstat[2] rc 0 nresetglobal 1: if the channel 2 generated an interrupt since last read of this register 5 cmpdstat[1] rc 0 nresetglobal 1: if the channel 1 generated an interrupt since last read of this register 4 cmpdstat[0] rc 0 nresetglobal 1: if the channel 0 generated an interrupt since last read of this register 3 cmpdout[3] r 0 nresetglobal channel 3 comparator output 2 cmpdout[2] r 0 nresetglobal channel 2 comparator output 1 cmpdout[1] r 0 nresetglobal channel 1 comparator output 0 cmpdout[0] r 0 nresetglobal channel 0 comparator output table 19-3: regcmpdstat pos. regcmpdctrl rw reset function 7 irqonrisingch[2] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channels 2 and 3. 0: an interrupt is generated on the falling edge of channels 2 and 3. 6 irqonrisingch[1] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channel 1. 0: an interrupt is generated on the falling edge of channel 1. 5 irqonrisingch[0] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channel 0. 0: an interrupt is generated on the falling edge of channel 0. 4 enirqch[3] rw 0 nresetglobal 1 enables interrupt on channel 3 3 enirqch[2] rw 0 nresetglobal 1 enables interrupt on channel 2 2 enirqch[1] rw 0 nresetglobal 1 enables interrupt on channel 1 1 enirqch[0] rw 0 nresetglobal 1 enables interrupt on channel 0 0 enable rw 0 nresetglobal enables the comparator table 19-4: regcmpdctrl 19.4 interrupt map interrupt source default mapping in the interrupt manager cmpd_irq regirqhigh[2] table 19-5: interrupt map
? semtech 2006 www.semtech.com 20-1 xe8806a/xe8807a 20 physical dimensions 20.1 so type package 20-2 20.2 qfp type package 20-3
? semtech 2006 www.semtech.com 20-2 xe8806a/xe8807a 20.1 so type package the so type package dimensions are give in figure 20-1 and table 20-1 figure 20-1. so type package package a inch (mm) b inch (mm) c inch (mm) d inch (mm) e inch (mm) f inch (mm) g inch (mm) so-24 0.606 (15.39 ) 0.294 (7.47) 0.1 (2.54) 0.007 (0.18) 0.017 (0.43) 0.05 (1.27) 0.01 (0.26) so-28 0.705 (17.90 ) 0.294 (7.47) 0.1 (2.54) 0.007 (0.18) 0.017 (0.43) 0.05 (1.27) 0.01 (0.26) table 20-1. so package dimensions
? semtech 2006 www.semtech.com 20-3 xe8806a/xe8807a 20.2 qfp type package the qfp package dimensions are given in figure 20-2 and table 20-2 figure 20-2. qfp type package package a inch (mm) b inch (mm) c inch (mm) d inch (mm) e inch (mm) f inch (mm) g inch (mm) tqfp-32 0.276 7.0 0.276 7.0 0.039 1.0 0.004 0.1 0.015 0.37 0.031 0.8 0.006 0.15 table 20-2. typical qfp package dimensions
? semtech 2006 www.semtech.com 20-4 xe8806a/xe8807a switzerland tel: 41-32-729-4000 fax: 41-32-729-4001 united kingdom tel: 44-1794-527-600 fax: 44-1794-527-601 france tel: 33-(0)169-28-22-00 fax: 33-(0)169-28-12-98 germany tel: 49-(0)8161-140-123 fax: 49-(0)8161-140-124 taiwan tel: 886-2-2748-3380 fax: 886-2-2748-3390 korea tel: 82-2-527-4377 fax: 82-2-527-4376 shanghai tel: 86-21-6391-0830 fax: 86-21-6391-0831 japan tel: 81-3-6408-0950 fax: 81-3-6408-0951 contact information semtech international ag is a wholly-owned subsidiary of semtech corporation, which has its headquarters in the u.s.a ? semtech 2005 all rights reserved. reproduction in whole or in part is prohibited wit hout the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contrac t, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of it s use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech. assume s no responsibility or liability w hatsoever for any failure or unexpected operat ion resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress in cluding, but not limited to, exposure to parameters beyond the spec ified maximum ratings or operat ion outside the s pecified range. semtech products are not designed, intended, auth orized or warranted to be suitable for use in life-support applications, devices or system s or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customer?s own risk. should a customer purchase or use semtech products fo r any such unauthoriz ed application, the customer shall indemnify and hold semtech and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

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